1 /* 2 * Copyright (c) 2007-2020 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 /* CMU_ENDHIST */ 32 /* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or [email protected] 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58 /* 59 */ 60 61 /* 62 * Processor registers for ARM 63 */ 64 #ifndef _ARM_PROC_REG_H_ 65 #define _ARM_PROC_REG_H_ 66 67 #if defined (__arm64__) 68 #include <pexpert/arm64/board_config.h> 69 #elif defined (__arm__) 70 #include <pexpert/arm/board_config.h> 71 #endif 72 73 #if defined (ARMA7) 74 #define __ARM_ARCH__ 7 75 #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k 76 #define __ARM_VMSA__ 7 77 #define __ARM_VFP__ 3 78 79 /* Force physical aperture to be mapped at PTE level so that its mappings 80 * can be updated to reflect cache attribute changes on alias mappings. This prevents 81 * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to 82 * an uncached alias mapping on the same core. Subsequent uncached writes from another 83 * core may not snoop this line, and the dirty line may end up being evicted later to 84 * effectively overwrite the uncached writes from other cores. */ 85 #define __ARM_PTE_PHYSMAP__ 1 86 /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than 87 * the xnu-managed processors may need to snoop our cache operations. 88 */ 89 #define __ARMA7_SMP__ 1 90 #define __ARM_COHERENT_CACHE__ 1 91 #define __ARM_DEBUG__ 7 92 #define __ARM_USER_PROTECT__ 1 93 #define __ARM_TIME_TIMEBASE_ONLY__ 1 94 95 #endif 96 97 #if __ARM_42BIT_PA_SPACE__ 98 /* For now, force the issue! */ 99 /* We need more VA space for the identity map to bootstrap the MMU */ 100 #undef __ARM64_PMAP_SUBPAGE_L1__ 101 #endif /* __ARM_42BIT_PA_SPACE__ */ 102 103 #if __ARM_KERNEL_PROTECT__ 104 /* 105 * This feature is not currently implemented for 32-bit ARM CPU architectures. 106 * A discussion of this feature for 64-bit ARM CPU architectures can be found 107 * in the ARM64 version of this file. 108 */ 109 #if __arm__ 110 #error __ARM_KERNEL_PROTECT__ is not supported on ARM32 111 #endif /* __arm__ */ 112 #endif /* __ARM_KERNEL_PROTECT__ */ 113 114 #if defined(ARM_BOARD_WFE_TIMEOUT_NS) 115 #define __ARM_ENABLE_WFE_ 1 116 #else /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */ 117 #define __ARM_ENABLE_WFE_ 0 118 #endif /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */ 119 120 /* For arm platforms, create one pset per cluster */ 121 #define MAX_PSETS MAX_CPU_CLUSTERS 122 123 /* 124 * The clutch scheduler is enabled only on non-AMP platforms for now. 125 */ 126 #if CONFIG_CLUTCH 127 128 #if __ARM_AMP__ 129 130 /* Enable the Edge scheduler for all J129 platforms */ 131 #if XNU_TARGET_OS_OSX 132 #define CONFIG_SCHED_CLUTCH 1 133 #define CONFIG_SCHED_EDGE 1 134 #endif /* XNU_TARGET_OS_OSX */ 135 136 #else /* __ARM_AMP__ */ 137 #define CONFIG_SCHED_CLUTCH 1 138 #endif /* __ARM_AMP__ */ 139 140 #endif /* CONFIG_CLUTCH */ 141 142 /* Thread groups are enabled on all ARM platforms (irrespective of scheduler) */ 143 #define CONFIG_THREAD_GROUPS 1 144 145 #ifdef XNU_KERNEL_PRIVATE 146 147 #if __ARM_VFP__ 148 #define ARM_VFP_DEBUG 0 149 #endif /* __ARM_VFP__ */ 150 151 #endif /* XNU_KERNEL_PRIVATE */ 152 153 154 155 /* 156 * FSR registers 157 * 158 * CPSR: Current Program Status Register 159 * SPSR: Saved Program Status Registers 160 * 161 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0 162 * +-----------------------------------------------------------+ 163 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE | 164 * +-----------------------------------------------------------+ 165 */ 166 167 /* 168 * Flags 169 */ 170 #define PSR_NF 0x80000000 /* Negative/Less than */ 171 #define PSR_ZF 0x40000000 /* Zero */ 172 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */ 173 #define PSR_VF 0x10000000 /* Overflow */ 174 #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */ 175 176 /* 177 * Modified execution mode flags 178 */ 179 #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */ 180 #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */ 181 #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */ 182 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */ 183 #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */ 184 185 /* 186 * Interrupts 187 */ 188 #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */ 189 #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */ 190 #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */ 191 192 /* 193 * CPU mode 194 */ 195 #define PSR_USER_MODE 0x00000010 /* User mode */ 196 #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */ 197 #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */ 198 #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */ 199 #define PSR_ABT_MODE 0x00000017 /* Abort mode */ 200 #define PSR_UND_MODE 0x0000001B /* Undefined mode */ 201 202 #define PSR_MODE_MASK 0x0000001F 203 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE) 204 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE) 205 206 #define PSR_USERDFLT PSR_USER_MODE 207 #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK) 208 #define PSR_USER_SET PSR_USER_MODE 209 210 #define PSR_INTMASK PSR_IRQF /* Interrupt disable */ 211 212 /* 213 * FPEXC: Floating-Point Exception Register 214 */ 215 216 #define FPEXC_EX 0x80000000 /* Exception status */ 217 #define FPEXC_EX_BIT 31 218 #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */ 219 #define FPEXC_EN_BIT 30 220 221 222 /* 223 * FPSCR: Floating-point Status and Control Register 224 */ 225 226 #define FPSCR_DN 0x02000000 /* Default NaN */ 227 #define FPSCR_FZ 0x01000000 /* Flush to zero */ 228 229 #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ 230 231 232 /* 233 * FSR registers 234 * 235 * IFSR: Instruction Fault Status Register 236 * DFSR: Data Fault Status Register 237 */ 238 #define FSR_ALIGN 0x00000001 /* Alignment */ 239 #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */ 240 #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */ 241 #define FSR_SFAULT 0x00000005 /* Translation Section */ 242 #define FSR_PFAULT 0x00000007 /* Translation Page */ 243 #define FSR_SACCESS 0x00000003 /* Section access */ 244 #define FSR_PACCESS 0x00000006 /* Page Access */ 245 #define FSR_SDOM 0x00000009 /* Domain Section */ 246 #define FSR_PDOM 0x0000000B /* Domain Page */ 247 #define FSR_SPERM 0x0000000D /* Permission Section */ 248 #define FSR_PPERM 0x0000000F /* Permission Page */ 249 #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */ 250 251 #define FSR_MASK 0x0000040F /* Valid bits */ 252 #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */ 253 254 #define DFSR_WRITE 0x00000800 /* write data abort fault */ 255 256 #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY) || defined (BCM2837) 257 258 #define TEST_FSR_VMFAULT(status) \ 259 (((status) == FSR_PFAULT) \ 260 || ((status) == FSR_PPERM) \ 261 || ((status) == FSR_SFAULT) \ 262 || ((status) == FSR_SPERM) \ 263 || ((status) == FSR_ICFAULT) \ 264 || ((status) == FSR_SACCESS) \ 265 || ((status) == FSR_PACCESS)) 266 267 #define TEST_FSR_TRANSLATION_FAULT(status) \ 268 (((status) == FSR_SFAULT) \ 269 || ((status) == FSR_PFAULT)) 270 271 #else 272 273 #error Incompatible CPU type configured 274 275 #endif 276 277 /* 278 * Cache configuration 279 */ 280 281 #if defined (ARMA7) 282 283 /* I-Cache */ 284 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */ 285 286 /* D-Cache */ 287 #define MMU_CSIZE 15 /* cache size as 1<<MMU_CSIZE (32K) */ 288 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 289 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */ 290 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ 291 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ 292 293 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ 294 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ 295 296 #define __ARM_L2CACHE__ 1 297 298 #define L2_CSIZE 20 /* cache size as 1<<MMU_CSIZE */ 299 #define L2_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 300 #define L2_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */ 301 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ 302 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ 303 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ 304 305 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<MMU_SWAY */ 306 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<MMU_NSET */ 307 308 #elif defined (APPLETYPHOON) 309 310 /* I-Cache */ 311 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 312 313 /* D-Cache */ 314 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 315 316 #elif defined (APPLETWISTER) 317 318 /* I-Cache */ 319 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 320 321 /* D-Cache */ 322 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 323 324 #elif defined (APPLEHURRICANE) 325 326 /* I-Cache */ 327 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 328 329 /* D-Cache */ 330 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 331 332 #elif defined (APPLEMONSOON) 333 334 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */ 335 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 336 337 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */ 338 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 339 340 #elif defined (APPLEVORTEX) 341 342 /* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */ 343 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 344 345 /* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */ 346 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 347 348 #elif defined (APPLELIGHTNING) 349 350 /* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */ 351 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 352 353 /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */ 354 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 355 356 #elif defined (APPLEFIRESTORM) 357 358 /* I-Cache, 256KB for Firestorm, 128KB for Icestorm, 6-way. */ 359 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 360 361 /* D-Cache, 160KB for Firestorm, 8-way. 64KB for Icestorm, 6-way. */ 362 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 363 364 #elif defined (BCM2837) /* Raspberry Pi 3 */ 365 366 /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */ 367 #define MMU_I_CLINE 6 368 369 /* D-Cache. */ 370 #define MMU_CLINE 6 371 372 #elif defined (VMAPPLE) 373 374 /* I-Cache. */ 375 #define MMU_I_CLINE 6 376 377 /* D-Cache. */ 378 #define MMU_CLINE 6 379 380 #else 381 #error processor not supported 382 #endif 383 384 #define MAX_L2_CLINE_BYTES (1 << MAX_L2_CLINE) 385 386 #if (__ARM_VMSA__ <= 7) 387 388 /* 389 * SCTLR: System Control Register 390 */ 391 /* 392 * System Control Register (SCTLR) 393 * 394 * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0 395 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+ 396 * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M| 397 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+ 398 * 399 * Where: 400 * TE: Thumb Exception enable 401 * AFE: Access flag enable 402 * TRE: TEX remap enable 403 * NMFI: Non-maskable FIQ (NMFI) support 404 * EE: Exception Endianness 405 * VE: Interrupt Vectors Enable 406 * FI: Fast interrupts configuration enable 407 * ITD: IT Disable 408 * UWXN: Unprivileged write permission implies PL1 XN 409 * WXN: Write permission implies XN 410 * HA: Hardware Access flag enable 411 * RR: Round Robin select 412 * V: High exception vectors 413 * I: Instruction cache enable 414 * Z: Branch prediction enable 415 * SW: SWP/SWPB enable 416 * C15BEN: CP15 barrier enable 417 * C: Cache enable 418 * A: Alignment check enable 419 * M: MMU enable 420 */ 421 422 #define SCTLR_RESERVED 0x82DD8394 423 424 #define SCTLR_ENABLE 0x00000001 /* MMU enable */ 425 #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */ 426 #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */ 427 #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */ 428 #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */ 429 #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */ 430 #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */ 431 #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */ 432 #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */ 433 #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */ 434 #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */ 435 #define SCTLR_TRE 0x10000000 /* TEX remap enable */ 436 #define SCTLR_AFE 0x20000000 /* Access flag enable */ 437 #define SCTLR_TE 0x40000000 /* Thumb Exception enable */ 438 439 #define SCTLR_DEFAULT \ 440 (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE) 441 442 443 /* 444 * PRRR: Primary Region Remap Register 445 * 446 * 31 24 20 19 18 17 16 0 447 * +---------------------------------------------------------------+ 448 * | NOSn | Res |NS1|NS0|DS1|DS0| TRn | 449 * +---------------------------------------------------------------+ 450 */ 451 452 #define PRRR_NS1 0x00080000 453 #define PRRR_NS0 0x00040000 454 #define PRRR_DS1 0x00020000 455 #define PRRR_DS0 0x00010000 456 457 #define PRRR_NOSn_ISH(region) (0x1<<((region)+24)) 458 459 #if defined (ARMA7) 460 #define PRRR_SETUP (0x1F08022A) 461 #else 462 #error processor not supported 463 #endif 464 465 /* 466 * NMRR, Normal Memory Remap Register 467 * 468 * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 469 * +---------------------------------------------------------------+ 470 * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0| 471 * +---------------------------------------------------------------+ 472 */ 473 474 #define NMRR_DISABLED 0x0 /* Non-cacheable */ 475 #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */ 476 #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */ 477 #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */ 478 479 #if defined (ARMA7) 480 #define NMRR_SETUP (0x01210121) 481 #else 482 #error processor not supported 483 #endif 484 485 /* 486 * TTBR: Translation Table Base Register 487 * 488 */ 489 490 #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */ 491 #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */ 492 #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */ 493 #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */ 494 495 #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */ 496 #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */ 497 #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */ 498 #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */ 499 500 #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */ 501 #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */ 502 503 #if defined (ARMA7) 504 #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED) 505 #else 506 #error processor not supported 507 #endif 508 509 /* 510 * TTBCR: Translation Table Base Control register 511 * 512 * 31 3 2 0 513 * +----------+ 514 * | zero | N | 515 * +----------+ 516 * 517 * If N=0, always use translation table base register 0. Otherwise, if 518 * bits [31:32-N] of the address are all zero use base register 0. Otherwise, 519 * use base register 1. 520 * 521 * Reading from this register also returns the page table boundary for TTB0. 522 * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...) 523 */ 524 525 #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */ 526 #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */ 527 #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */ 528 #define TTBCR_N_MASK 0x3 529 530 #define TTBCR_N_SETUP (TTBCR_N_2GB_TTB0) 531 532 533 534 /* 535 * ARM Page Granule 536 */ 537 #define ARM_PGSHIFT 12 538 #define ARM_PGBYTES (1 << ARM_PGSHIFT) 539 #define ARM_PGMASK (ARM_PGBYTES-1) 540 541 /* 542 * DACR: Domain Access Control register 543 */ 544 545 #define DAC_FAULT 0x0 /* invalid domain - everyone loses */ 546 #define DAC_CLIENT 0x1 /* client domain - use AP bits */ 547 #define DAC_RESERVE 0x2 /* reserved domain - undefined */ 548 #define DAC_MANAGER 0x3 /* manager domain - all access */ 549 550 #define DACR_SET(dom, x) ((x)<<((dom)<<1)) 551 552 553 #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */ 554 #define ARM_DAC_SETUP 0x1 555 556 /* 557 * ARM 2-level Page Table support 558 */ 559 560 /* 561 * Memory Attribute Index 562 */ 563 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */ 564 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */ 565 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */ 566 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */ 567 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */ 568 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE 569 #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE 570 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED CACHE_ATTRINDX_DISABLE 571 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 572 573 574 /* 575 * Access protection bit values 576 */ 577 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */ 578 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */ 579 #define AP_RONA 0x2 /* priv=read-only , user=no-access */ 580 #define AP_RORO 0x3 /* priv=read-only , user=read-only */ 581 582 /* 583 * L1 Translation table 584 * 585 * Each translation table is up to 16KB 586 * 4096 32-bit entries of 1MB of address space. 587 */ 588 589 #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */ 590 #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */ 591 #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */ 592 #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */ 593 #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */ 594 #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */ 595 #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */ 596 597 #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */ 598 #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1) 599 600 /* 601 * L2 Translation table 602 * 603 * Each translation table is up to 1KB 604 * 256 32-bit entries of 4KB (2^12) of address space. 605 */ 606 607 #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */ 608 #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */ 609 #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */ 610 #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */ 611 612 /* 613 * Convenience definitions for: 614 * ARM_TT_LEAF: The last level of the configured page table format. 615 * ARM_TT_TWIG: The second to last level of the configured page table format. 616 * ARM_TT_ROOT: The first level of the configured page table format. 617 * 618 * My apologies to any botanists who may be reading this. 619 */ 620 #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE 621 #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK 622 #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT 623 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK 624 625 #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE 626 #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK 627 #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT 628 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK 629 630 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE 631 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK 632 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT 633 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK 634 635 /* 636 * Level 1 Translation Table Entry 637 * 638 * page table entry 639 * 640 * 31 10 9 8 5 4 2 0 641 * +----------------------+-+----+--+--+--+ 642 * | page table base addr | |dom |XN|00|01| 643 * +----------------------+-+----+--+--+--+ 644 * 645 * direct (1MB) section entry 646 * 647 * 31 20 18 15 12 10 9 8 5 4 2 0 648 * +------------+--+-+-+-+---+--+-+----+--+--+--+ 649 * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10| 650 * +------------+--+-+-+-+---+--+-+----+--+--+--+ 651 * 652 * super (16MB) section entry 653 * 654 * 31 24 23 18 15 12 10 9 8 5 4 2 0 655 * +---------+------+-+-+-+---+--+-+----+--+--+--+ 656 * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10| 657 * +---------+------+-+-+-+---+--+-+----+--+--+--+ 658 * 659 * where: 660 * 'G' is the notGlobal bit 661 * 'S' is the shared bit 662 * 'A' in the access permission extension (APX) bit 663 * 'TEX' remap register control bits 664 * 'AP' is the access protection 665 * 'dom' is the domain for the translation 666 * 'XN' is the eXecute Never bit 667 * 'CB' is the cache/buffer attribute 668 */ 669 670 #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */ 671 672 #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */ 673 #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */ 674 #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */ 675 #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */ 676 677 #define ARM_TTE_BLOCK_NGSHIFT 17 678 #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */ 679 #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */ 680 681 #define ARM_TTE_BLOCK_SHSHIFT 16 682 #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */ 683 #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */ 684 685 #define ARM_TTE_BLOCK_CBSHIFT 2 686 #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT) 687 #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT) 688 689 #define ARM_TTE_BLOCK_AP0SHIFT 10 690 #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT) 691 #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT) 692 693 #define ARM_TTE_BLOCK_AP1SHIFT 11 694 #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT) 695 #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT) 696 697 #define ARM_TTE_BLOCK_AP2SHIFT 15 698 #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT) 699 #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT) 700 701 /* access protections */ 702 #define ARM_TTE_BLOCK_AP(ap) \ 703 ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) | \ 704 ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT)) 705 706 /* mask access protections */ 707 #define ARM_TTE_BLOCK_APMASK \ 708 (ARM_TTE_BLOCK_AP1_MASK | ARM_TTE_BLOCK_AP2_MASK) 709 710 #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */ 711 #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */ 712 713 #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */ 714 #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */ 715 716 #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */ 717 #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */ 718 719 #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */ 720 #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */ 721 722 #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */ 723 #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */ 724 725 #define ARM_TTE_BLOCK_NXSHIFT 4 726 #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */ 727 #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */ 728 #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX 729 730 #define ARM_TTE_BLOCK_TEX0SHIFT 12 731 #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT) 732 #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT) 733 734 #define ARM_TTE_BLOCK_TEX1SHIFT 13 735 #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT) 736 #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT) 737 738 #define ARM_TTE_BLOCK_TEX2SHIFT 14 739 #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT) 740 #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT) 741 742 743 /* mask memory attributes index */ 744 #define ARM_TTE_BLOCK_ATTRINDX(i) \ 745 ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) | \ 746 ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT)) 747 748 /* mask memory attributes index */ 749 #define ARM_TTE_BLOCK_ATTRINDXMASK \ 750 (ARM_TTE_BLOCK_CB_MASK | ARM_TTE_BLOCK_TEX0_MASK) 751 752 753 /* 754 * Level 2 Page table entries 755 * 756 * The following page table entry types are possible: 757 * 758 * fault page entry 759 * 31 2 0 760 * +----------------------------------------+--+ 761 * | ignored |00| 762 * +----------------------------------------+--+ 763 * 764 * large (64KB) page entry 765 * 31 16 15 12 9 6 4 3 2 0 766 * +----------------+--+---+-+-+-+---+--+-+-+--+ 767 * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01| 768 * +----------------+--+---+-+-+-+---+--+-+-+--+ 769 * 770 * small (4KB) page entry 771 * 31 12 9 6 4 3 2 1 0 772 * +-----------------------+-+-+-+---+--+-+-+-+--+ 773 * | base phys addr |G|S|A|TEX|AP|C|B|1|XN| 774 * +-----------------------+-+-+-+---+--+-+-+-+--+ 775 * 776 * also where: 777 * 'XN' is the eXecute Never bit 778 * 'G' is the notGlobal (process-specific) bit 779 * 'S' is the shared bit 780 * 'A' in the access permission extension (ATX) bit 781 * 'TEX' remap register control bits 782 * 'AP' is the access protection 783 * 'dom' is the domain for the translation 784 * 'C' is the cache attribute 785 * 'B' is the write buffer attribute 786 */ 787 788 /* markers for (invalid) PTE for a page sent to compressor */ 789 #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */ 790 #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */ 791 #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT) 792 #define ARM_PTE_IS_COMPRESSED(x, p) \ 793 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \ 794 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \ 795 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \ 796 (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \ 797 (p), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE))) 798 799 #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */ 800 #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */ 801 802 #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */ 803 804 #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */ 805 #define ARM_PTE_TYPE_VALID 0x00000002 /* valid L2 entry */ 806 #define ARM_PTE_TYPE 0x00000002 /* small page entry type */ 807 #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */ 808 809 #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */ 810 #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */ 811 812 #define ARM_PTE_SHSHIFT 10 813 #define ARM_PTE_SHMASK 0x00000400 /* shared (SMP) mapping mask */ 814 #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */ 815 816 #define ARM_PTE_CBSHIFT 2 817 #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT) 818 #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT) 819 820 #define ARM_PTE_AP0SHIFT 4 821 #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT) 822 #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT) 823 824 #define ARM_PTE_AP1SHIFT 5 825 #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT) 826 #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT) 827 828 #define ARM_PTE_AP2SHIFT 9 829 #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT) 830 #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT) 831 832 /* access protections */ 833 #define ARM_PTE_AP(ap) \ 834 ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) | \ 835 ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT)) 836 837 /* mask access protections */ 838 #define ARM_PTE_APMASK \ 839 (ARM_PTE_AP1_MASK | ARM_PTE_AP2_MASK) 840 841 #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */ 842 #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */ 843 844 #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */ 845 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */ 846 847 #define ARM_PTE_NXSHIFT 0 848 #define ARM_PTE_NX 0x00000001 /* small page no execute */ 849 #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT) 850 851 #define ARM_PTE_PNXSHIFT 0 852 #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */ 853 #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT) 854 855 #define ARM_PTE_XMASK (ARM_PTE_PNX_MASK | ARM_PTE_NX_MASK) 856 857 #define ARM_PTE_TEX0SHIFT 6 858 #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT) 859 #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT) 860 861 #define ARM_PTE_TEX1SHIFT 7 862 #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT) 863 #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT) 864 865 #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT 866 #define ARM_PTE_WRITEABLE ARM_PTE_TEX1 867 #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK 868 869 #define ARM_PTE_TEX2SHIFT 8 870 #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT) 871 #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT) 872 873 #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT 874 #define ARM_PTE_WIRED ARM_PTE_TEX2 875 #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK 876 877 /* mask memory attributes index */ 878 #define ARM_PTE_ATTRINDX(indx) \ 879 ((((indx)&0x3)<<ARM_PTE_CBSHIFT) | \ 880 ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT)) 881 882 /* mask memory attributes index */ 883 #define ARM_PTE_ATTRINDXMASK \ 884 (ARM_PTE_CB_MASK | ARM_PTE_TEX0_MASK) 885 886 #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */ 887 #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */ 888 #define ARM_SECTION_SIZE (1024*1024) /* 1MB */ 889 #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */ 890 891 #define TLBI_ADDR_SHIFT (12) 892 #define TLBI_ADDR_SIZE (20) 893 #define TLBI_ADDR_MASK (((1ULL << TLBI_ADDR_SIZE) - 1)) 894 #define TLBI_ASID_SHIFT (0) 895 #define TLBI_ASID_SIZE (8) 896 #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1)) 897 #endif 898 899 /* 900 * Format of the Debug Status and Control Register (DBGDSCR) 901 */ 902 #define ARM_DBGDSCR_RXFULL (1 << 30) 903 #define ARM_DBGDSCR_TXFULL (1 << 29) 904 #define ARM_DBGDSCR_RXFULL_1 (1 << 27) 905 #define ARM_DBGDSCR_TXFULL_1 (1 << 26) 906 #define ARM_DBGDSCR_PIPEADV (1 << 25) 907 #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24) 908 #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20) 909 #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20) 910 #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20) 911 #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20) 912 #define ARM_DBGDSCR_ADADISCARD (1 << 19) 913 #define ARM_DBGDSCR_NS (1 << 18) 914 #define ARM_DBGDSCR_SPNIDDIS (1 << 17) 915 #define ARM_DBGDSCR_SPIDDIS (1 << 16) 916 #define ARM_DBGDSCR_MDBGEN (1 << 15) 917 #define ARM_DBGDSCR_HDBGEN (1 << 14) 918 #define ARM_DBGDSCR_ITREN (1 << 13) 919 #define ARM_DBGDSCR_UDCCDIS (1 << 12) 920 #define ARM_DBGDSCR_INTDIS (1 << 11) 921 #define ARM_DBGDSCR_DBGACK (1 << 10) 922 #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9) 923 #define ARM_DBGDSCR_UND_1 (1 << 8) 924 #define ARM_DBGDSCR_ADABORT_1 (1 << 7) 925 #define ARM_DBGDSCR_SDABORT_1 (1 << 6) 926 #define ARM_DBGDSCR_MOE_MASK (15 << 2) 927 #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2) 928 #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2) 929 #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2) 930 #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2) 931 #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2) 932 #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2) 933 #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2) 934 #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2) 935 #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2) 936 #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2) 937 938 #define ARM_DBGDSCR_RESTARTED (1 << 1) 939 #define ARM_DBGDSCR_HALTED (1 << 0) 940 941 /* 942 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers 943 * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible 944 */ 945 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */ 946 #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */ 947 948 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */ 949 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */ 950 #define ARM_DBGBCR_MATCH_MATCH (0 << 22) 951 #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22) 952 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */ 953 #define ARM_DBGBCR_TYPE_IVA (0 << 21) 954 #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21) 955 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */ 956 #define ARM_DBG_CR_LINKED_LINKED (1 << 20) 957 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20) 958 #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */ 959 #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */ 960 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14) 961 #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14) 962 #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14) 963 #define ARM_DBG_CR_HIGHER_MODE_MASK (1 << 13) /* BCR & WCR */ 964 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13) 965 #define ARM_DBG_CR_HIGHER_MODE_DISABLE (0 << 13) 966 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */ 967 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */ 968 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */ 969 #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3) 970 #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3) 971 #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3) 972 #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */ 973 #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */ 974 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */ 975 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */ 976 #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */ 977 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */ 978 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0) 979 #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0) 980 981 /* 982 * Format of the Device Power-down and Reset Status Register (DBGPRSR) 983 */ 984 #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3) 985 #define ARM_DBGPRSR_RESET_STATUS (1 << 2) 986 #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1) 987 #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0) 988 989 /* 990 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR) 991 */ 992 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55 993 994 /* ARMv7 Debug register map */ 995 #define ARM_DEBUG_OFFSET_DBGDIDR (0x000) 996 #define ARM_DEBUG_OFFSET_DBGWFAR (0x018) 997 #define ARM_DEBUG_OFFSET_DBGVCR (0x01C) 998 #define ARM_DEBUG_OFFSET_DBGECR (0x024) 999 #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028) 1000 #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C) 1001 #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080) 1002 #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */ 1003 #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */ 1004 #define ARM_DEBUG_OFFSET_DBGDSCR (0x088) 1005 #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C) 1006 #define ARM_DEBUG_OFFSET_DBGDRCR (0x090) 1007 #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */ 1008 #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */ 1009 #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */ 1010 #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */ 1011 #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300) 1012 #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304) 1013 #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308) 1014 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310) 1015 #define ARM_DEBUG_OFFSET_DBGPRSR (0x314) 1016 #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00) 1017 #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0) 1018 #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4) 1019 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0) 1020 #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4) 1021 #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8) 1022 #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8) 1023 #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC) 1024 #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0) 1025 #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4) 1026 #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8) 1027 #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA) 1028 #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC) 1029 #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0) 1030 #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4) 1031 #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8) 1032 #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA) 1033 #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC) 1034 1035 /* 1036 * Media and VFP Feature Register 1 (MVFR1) 1037 */ 1038 #define MVFR_ASIMD_HPFP 0x00100000UL 1039 1040 /* 1041 * Main ID Register (MIDR) 1042 * 1043 * 31 24 23 20 19 16 15 4 3 0 1044 * +-----+-----+------+------+-----+ 1045 * | IMP | VAR | ARCH | PNUM | REV | 1046 * +-----+-----+------+------+-----+ 1047 * 1048 * where: 1049 * IMP: Implementor code 1050 * VAR: Variant number 1051 * ARCH: Architecture code 1052 * PNUM: Primary part number 1053 * REV: Minor revision number 1054 */ 1055 #define MIDR_REV_SHIFT 0 1056 #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT) 1057 #define MIDR_PNUM_SHIFT 4 1058 #define MIDR_PNUM_MASK (0xfff << MIDR_PNUM_SHIFT) 1059 #define MIDR_ARCH_SHIFT 16 1060 #define MIDR_ARCH_MASK (0xf << MIDR_ARCH_SHIFT) 1061 #define MIDR_VAR_SHIFT 20 1062 #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT) 1063 #define MIDR_IMP_SHIFT 24 1064 #define MIDR_IMP_MASK (0xff << MIDR_IMP_SHIFT) 1065 1066 #ifdef __arm__ 1067 1068 /* Macros meant to make __builtin_arm_* functions easier to use. */ 1069 #define MRC_SCTLR 15,0,1,0,0 1070 #define MCR_SCTLR(x) 15,0,(x),1,0,0 1071 1072 #define MRC_ACTLR 15,0,1,0,1 1073 #define MCR_ACTLR(x) 15,0,(x),1,0,1 1074 1075 #endif /* __arm__ */ 1076 1077 1078 #endif /* _ARM_PROC_REG_H_ */ 1079