1 /* 2 * Copyright (c) 2019 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 29 #ifndef _PEXPERT_ARM64_H14_H 30 #define _PEXPERT_ARM64_H14_H 31 32 #define APPLEAVALANCHE 33 #define NO_MONITOR 1 /* No EL3 for this CPU -- ever */ 34 #define HAS_CTRR 1 /* Has CTRR registers */ 35 #define HAS_NEX_PG 1 /* Supports p-Core NEX powergating during Neon inactivity */ 36 #define HAS_BP_RET 1 /* Supports branch predictor state retention across ACC sleep */ 37 #define HAS_CONTINUOUS_HWCLOCK 1 /* Has a hardware clock that ticks during sleep */ 38 #define HAS_IPI 1 /* Has IPI registers */ 39 #define HAS_CLUSTER 1 /* Has eCores and pCores in separate clusters */ 40 #define HAS_RETENTION_STATE 1 /* Supports architectural state retention */ 41 42 43 #define HAS_UCNORMAL_MEM 1 /* Supports completely un-cacheable normal memory type */ 44 #define HAS_FAST_CNTVCT 1 45 #define HAS_ACNTVCT 1 /* Supports private ISA non speculative MRS reads of timebase registers (ACNTPCT/ACNTVCT) */ 46 47 48 #define HAS_USAT_BIT 1 /* ACTLR has USAT bit (H12+) */ 49 #define HAS_ARM_FEAT_SSBS2 1 /* Supports Speculative Store Bypass Safe with MSR controls */ 50 #define HAS_E0PD 1 /* Supports E0PD0 and E0PD1 in TCR for Meltdown mitigation (ARMv8.5)*/ 51 52 53 #define HAS_ACFG 1 /* Supports ACFG_EL1 system register */ 54 #define HAS_AMDSCR 1 /* Supports AMDSCR_EL1 system register */ 55 #define HAS_HCR_TSC_RW 1 /* HCR_EL2.TSC is writable */ 56 #define HAS_CPU_DPE_COUNTER 1 /* Has a hardware counter for digital power estimation */ 57 58 #define CPU_HAS_APPLE_PAC 1 59 #define HAS_UNCORE_CTRS 1 60 #define UNCORE_VERSION 2 61 #define UNCORE_PER_CLUSTER 1 62 #define UNCORE_NCTRS 16 63 #define CORE_NCTRS 10 64 #define HAS_CPMU_PC_CAPTURE 1 65 66 /* Performance Monitor */ 67 #define CPMU_PMC_COUNT 10 68 #define CPMU_INSTRUCTION_MATCHING 1 69 #define CPMU_MEMORY_FILTERING 1 70 #define CPMU_64BIT_PMCS 1 71 #define HAS_UPMU 1 72 #define UPMU_VERSION 2 73 #define UPMU_PMC_COUNT 16 74 #define UPMU_PER_CLUSTER 1 75 #define UPMU_AF_LATENCY 1 76 #define UPMU_META_EVENTS 1 77 #define UPMU_64BIT_PMCS 1 78 79 #define __ARM_AMP__ 1 80 #define __ARM_16K_PG__ 1 81 #define __ARM_GLOBAL_SLEEP_BIT__ 1 82 #define __ARM_PAN_AVAILABLE__ 1 83 #define __ARM_SB_AVAILABLE__ 1 84 85 86 87 88 #define __HWP_CFG_BIT_VER__ 2 89 90 /* Optional CPU features -- an SoC may #undef these */ 91 92 #define ARM_PARAMETERIZED_PMAP 1 93 #define __ARM_MIXED_PAGE_SIZE__ 1 94 95 96 #define __ARM_RANGE_TLBI__ 1 97 98 #include <pexpert/arm64/vhe_disable.h> 99 100 #include <pexpert/arm64/apple_arm64_common.h> 101 102 #endif /* !_PEXPERT_ARM64_H14_H */ 103