1 // Copyright (c) 2020 Apple Inc. All rights reserved. 2 // 3 // @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 4 // 5 // This file contains Original Code and/or Modifications of Original Code 6 // as defined in and that are subject to the Apple Public Source License 7 // Version 2.0 (the 'License'). You may not use this file except in 8 // compliance with the License. The rights granted to you under the License 9 // may not be used to create, or enable the creation or redistribution of, 10 // unlawful or unlicensed copies of an Apple operating system, or to 11 // circumvent, violate, or enable the circumvention or violation of, any 12 // terms of an Apple operating system software license agreement. 13 // 14 // Please obtain a copy of the License at 15 // http://www.opensource.apple.com/apsl/ and read it before using this file. 16 // 17 // The Original Code and all software distributed under the License are 18 // distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 19 // EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 20 // INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 21 // FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 22 // Please see the License for the specific language governing rights and 23 // limitations under the License. 24 // 25 // @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 26 27 #ifndef PERFMON_ARM64_REGS_H 28 #define PERFMON_ARM64_REGS_H 29 30 #if KERNEL 31 #include <pexpert/arm64/board_config.h> 32 #endif // KERNEL 33 34 // Store the register list in a macro, as it needs to both describe each 35 // register (as a string name) and sample them, preserving the list order. The 36 // MSR builtins require string literals, limiting the ability to avoid macros. 37 // 38 // The source file that includes this header is responsible for defining the 39 // following macros to generate the PMC and register lists: 40 // 41 // - PMC 42 // - REG 43 #if HAS_UPMU 44 // - UPMC 45 // - PIOREG 46 #endif // HAS_UPMU 47 48 // Core Perfrormance Monitoring Unit Registers. 49 50 #define CPMU_PMCS_BASE PMC(0) PMC(1) PMC(2) PMC(3) PMC(4) PMC(5) PMC(6) PMC(7) 51 52 #if CPMU_PMC_COUNT > 8 53 #define CPMU_PMCS CPMU_PMCS_BASE PMC(8) PMC(9) 54 #else // CPMU_PMC_COUNT > 8 55 #define CPMU_PMCS CPMU_PMCS_BASE 56 #endif // CPMU_PMC_COUNT <= 8 57 58 // Only read MSRs that are supported for this hardware. clang will abort if it 59 // sees an MSR that's not present in its machine model. 60 61 #if CPMU_MEMORY_FILTERING 62 #define MEMFLT_REGS REG(PM_MEMFLT_CTL23) REG(PM_MEMFLT_CTL45) 63 #else // CPMU_MEMORY_FILTERING 64 #define MEMFLT_REGS 65 #endif // !CPMU_MEMORY_FILTERING 66 #if CPMU_INSTRUCTION_MATCHING 67 #define BP_REGS REG(PMCR_BVRNG4) REG(PMCR_BVRNG5) 68 #else // CPMU_INSTRUCTION_MATCHING 69 #define BP_REGS 70 #endif // !CPMU_INSTRUCTION_MATCHING 71 72 #define META_REGS REG(PMMMAP) 73 #define USER_CTL_REGS REG(PMCR2) REG(PMCR3) REG(PMCR4) 74 #define OPMATCH_REGS REG(OPMAT0) REG(OPMAT1) 75 76 #define CPMU_REGS \ 77 REG(PMCR0) REG(PMCR1) USER_CTL_REGS \ 78 REG(PMESR0) REG(PMESR1) REG(PMSR) \ 79 OPMATCH_REGS BP_REGS MEMFLT_REGS META_REGS CPMU_PMCS 80 81 #define CPMU_ATTR_REGS \ 82 USER_CTL_REGS OPMATCH_REGS BP_REGS MEMFLT_REGS META_REGS 83 84 #if HAS_UPMU 85 86 // Uncore Perfmormance Monitoring Unit Registers. 87 88 #define UPMU_PMCS_BASE \ 89 UPMC(0, 0x4100) UPMC(1, 0x4248) UPMC(2, 0x4110) UPMC(3, 0x4250) \ 90 UPMC(4, 0x4120) UPMC(5, 0x4258) UPMC(6, 0x4130) UPMC(7, 0x4260) 91 92 #if UPMU_PMC_COUNT > 8 93 #define UPMU_PMCS \ 94 UPMU_PMCS_BASE UPMC(8, 0x4140) UPMC(9, 0x4268) UPMC(10, 0x4150) \ 95 UPMC(11, 0x4270) UPMC(12, 0x4160) UPMC(13, 0x4278) UPMC(14, 0x4170) \ 96 UPMC(15, 0x4280) 97 #else // UPMU_PMC_COUNT > 8 98 #define UPMU_PMCS UPMU_PMCS_BASE 99 #endif // UPMU_PMC_COUNT <= 8 100 101 // TODO UPMPCM is ACC_IMPL-relative in version 2. 102 103 #if UPMU_AF_LATENCY 104 #define AFLAT_REGS \ 105 PIOREG(AFLATCTL1, 0x41d0) PIOREG(AFLATCTL2, 0x41d8) \ 106 PIOREG(AFLATCTL3, 0x41e0) PIOREG(AFLATCTL4, 0x41e8) \ 107 PIOREG(AFLATCTL5, 0x41f0) \ 108 PIOREG(AFLATVALBIN0, 0x4208) PIOREG(AFLATVALBIN1, 0x4210) \ 109 PIOREG(AFLATVALBIN2, 0x4218) PIOREG(AFLATVALBIN3, 0x4220) \ 110 PIOREG(AFLATVALBIN4, 0x4228) PIOREG(AFLATVALBIN5, 0x4230) \ 111 PIOREG(AFLATVALBIN6, 0x4238) PIOREG(AFLATVALBIN7, 0x4240) \ 112 PIOREG(AFLATINFLO, 0x4288) PIOREG(AFLATINFHI, 0x4290) 113 #else // UPMU_AF_LATENCY 114 #define AFLAT_REGS 115 #endif // !UPMU_AF_LATENCY 116 117 #if UPMU_PMC_COUNT > 8 118 #define UPMESR1 PIOREG(UPMESR1, 0x41b8) 119 #define UPMU_16_REGS UPMESR1 PIOREG(UPMCR1, 0x4188) 120 #else // UPMU_PMC_COUNT > 8 121 #define UPMU_16_REGS 122 #endif // UPMU_PMC_COUNT <= 8 123 124 #define ECM_REGS_BASE PIOREG(UPMECM0, 0x4190) PIOREG(UPMECM1, 0x4198) 125 #if UPMU_PMC_COUNT > 8 126 #define ECM_REGS ECM_REGS_BASE PIOREG(UPMECM2, 0x41a0) PIOREG(UPMECM3, 0x41a8) 127 #else // UPMU_PMC_COUNT > 8 128 #define ECM_REGS ECM_REGS_BASE 129 #endif // UPMU_PMC_COUNT <= 8 130 131 #if UPMU_META_EVENTS 132 #define UMETA_REGS \ 133 PIOREG(UPMCFILTER0, 0x0600) PIOREG(UPMCFILTER1, 0x0608) \ 134 PIOREG(UPMCFILTER2, 0x0610) PIOREG(UPMCFILTER3, 0x0618) \ 135 PIOREG(UPMCFILTER4, 0x0620) PIOREG(UPMCFILTER5, 0x0628) \ 136 PIOREG(UPMCFILTER6, 0x0630) PIOREG(UPMCFILTER7, 0x0638) 137 #else // UPMU_META_EVENTS 138 #define UMETA_REGS 139 #endif // !UPMU_META_EVENTS 140 141 #define UPMCR0 PIOREG(UPMCR0, 0x4180) 142 #define UPMESR0 PIOREG(UPMESR0, 0x41b0) 143 144 #define UPMU_REGS UPMCR0 UPMESR0 UPMU_16_REGS ECM_REGS AFLAT_REGS UPMU_PMCS 145 146 #define UPMU_ATTR_REGS ECM_REGS AFLAT_REGS 147 148 #endif // HAS_UPMU 149 150 #endif // !defined(PERFMON_ARM64_REGS_H) 151