1 /* 2 * Copyright (c) 2012-2015 Apple Inc. All rights reserved. 3 */ 4 5 #ifndef _PEXPERT_ARM64_COMMON_H 6 #define _PEXPERT_ARM64_COMMON_H 7 8 /* This block of definitions is misplaced to shelter it from lines that will be 9 * removed in rdar://56937184. These definitions must be moved back after that 10 * change has been merged. */ 11 #ifdef APPLE_ARM64_ARCH_FAMILY 12 #endif 13 14 #ifdef ASSEMBLER 15 #define __MSR_STR(x) x 16 #else 17 #define __MSR_STR1(x) #x 18 #define __MSR_STR(x) __MSR_STR1(x) 19 #endif 20 21 #ifdef APPLE_ARM64_ARCH_FAMILY 22 23 24 25 #if defined(APPLETYPHOON) || defined(APPLETWISTER) 26 #define ARM64_REG_CYC_CFG_skipInit (1ULL<<30) 27 #define ARM64_REG_CYC_CFG_deepSleep (1ULL<<24) 28 #else /* defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER) */ 29 #define ARM64_REG_ACC_OVRD_enDeepSleep (1ULL << 34) 30 #define ARM64_REG_ACC_OVRD_disPioOnWfiCpu (1ULL << 32) 31 #define ARM64_REG_ACC_OVRD_dsblClkDtr (1ULL << 29) 32 #define ARM64_REG_ACC_OVRD_cpmWakeUp_mask (3ULL << 27) 33 #define ARM64_REG_ACC_OVRD_cpmWakeUp_force (3ULL << 27) 34 #define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_mask (3ULL << 25) 35 #define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deny (2ULL << 25) 36 #define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deepsleep (3ULL << 25) 37 #define ARM64_REG_ACC_OVRD_ok2TrDnLnk_mask (3ULL << 17) 38 #define ARM64_REG_ACC_OVRD_ok2TrDnLnk_deepsleep (3ULL << 17) 39 #define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_mask (3ULL << 15) 40 #define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_deepsleep (2ULL << 15) 41 #define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_mask (3ULL << 13) 42 #define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_deepsleep (3ULL << 13) 43 #endif /* defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER) */ 44 45 #define ARM64_REG_CYC_OVRD_irq_mask (3<<22) 46 #define ARM64_REG_CYC_OVRD_irq_disable (2<<22) 47 #define ARM64_REG_CYC_OVRD_fiq_mask (3<<20) 48 #define ARM64_REG_CYC_OVRD_fiq_disable (2<<20) 49 #define ARM64_REG_CYC_OVRD_ok2pwrdn_force_up (2<<24) 50 #define ARM64_REG_CYC_OVRD_ok2pwrdn_force_down (3<<24) 51 #define ARM64_REG_CYC_OVRD_disWfiRetn (1<<0) 52 53 #if defined(APPLEMONSOON) 54 #define ARM64_REG_CYC_OVRD_dsblSnoopTime_mask (3ULL << 30) 55 #define ARM64_REG_CYC_OVRD_dsblSnoopPTime (1ULL << 31) /// Don't fetch the timebase from the P-block 56 #endif /* APPLEMONSOON */ 57 58 #define ARM64_REG_LSU_ERR_STS_L1DTlbMultiHitEN (1ULL<<54) 59 #define ARM64_REG_LSU_ERR_CTL_L1DTlbMultiHitEN (1ULL<<3) 60 61 62 63 #if defined(HAS_IPI) 64 #define ARM64_REG_IPI_RR_TYPE_IMMEDIATE (0 << 28) 65 #define ARM64_REG_IPI_RR_TYPE_RETRACT (1 << 28) 66 #define ARM64_REG_IPI_RR_TYPE_DEFERRED (2 << 28) 67 #define ARM64_REG_IPI_RR_TYPE_NOWAKE (3 << 28) 68 69 #define ARM64_IPISR_IPI_PENDING (1ull << 0) 70 #endif /* defined(HAS_IPI) */ 71 72 #if defined(HAS_OBJC_BP_HELPER) 73 #define ARM64_REG_BP_OBJC_ADR_EL1_mask (0x00ffffffffffffffull) 74 #define ARM64_REG_BP_OBJC_ADR_EL1_shift (0) 75 76 #define ARM64_REG_BP_OBJC_CTL_EL1_Mask_mask (0x001ffffff8000000ull) 77 #define ARM64_REG_BP_OBJC_CTL_EL1_Mask_shift (27) 78 79 #define ARM64_REG_BP_OBJC_CTL_EL1_AR_ClassPtr_mask (0x00000000003e0000ull) 80 #define ARM64_REG_BP_OBJC_CTL_EL1_AR_ClassPtr_shift (17) 81 82 #define ARM64_REG_BP_OBJC_CTL_EL1_AR_Selector_mask (0x000000000001f000ull) 83 #define ARM64_REG_BP_OBJC_CTL_EL1_AR_Selector_shift (12) 84 85 #define ARM64_REG_BP_OBJC_CTL_EL1_Br_Offset_mask (0x000000000000007full) 86 #define ARM64_REG_BP_OBJC_CTL_EL1_Br_Offset_shift (0) 87 #endif /* defined(HAS_OBJC_BP_HELPER) */ 88 89 90 #endif /* APPLE_ARM64_ARCH_FAMILY */ 91 92 93 #if defined(HAS_BP_RET) 94 #define ARM64_REG_ACC_CFG_bdpSlpEn (1ULL << 2) 95 #define ARM64_REG_ACC_CFG_btpSlpEn (1ULL << 3) 96 #define ARM64_REG_ACC_CFG_bpSlp_mask 3 97 #define ARM64_REG_ACC_CFG_bpSlp_shift 2 98 #endif /* defined(HAS_BP_RET) */ 99 100 101 102 #define MPIDR_CORETYPE_SHIFT (16) 103 #define MPIDR_CORETYPE_WIDTH (3) 104 #define MPIDR_CORETYPE_MASK ((1ULL << MPIDR_CORETYPE_WIDTH) - 1) 105 #define MPIDR_CORETYPE_ACC_E (0ULL) 106 #define MPIDR_CORETYPE_ACC_P (1ULL) 107 108 109 110 #define CPU_PIO_CPU_STS_OFFSET (0x100ULL) 111 #define CPU_PIO_CPU_STS_cpuRunSt_mask (0xff) 112 113 /* 114 * CORE_THRTL_CFG2 non-sysreg tunable 115 */ 116 #define CORE_THRTL_CFG2_OFFSET (0x218) 117 118 #define CORE_THRTL_CFG2_c1pptThrtlRate_shift (56) 119 #define CORE_THRTL_CFG2_c1pptThrtlRate_mask (0xFFULL << CORE_THRTL_CFG2_c1pptThrtlRate_shift) 120 121 122 123 124 #ifdef ASSEMBLER 125 126 /* 127 * Determines whether the executing core is a P-core. 128 * 129 * @param arg0 result register; will be non-zero if executed on a P-core, else 130 * zero if executed on an E-core / non-PE core / non-AMP architectures. 131 */ 132 .macro ARM64_IS_PCORE 133 #if defined(APPLEMONSOON) || HAS_CLUSTER 134 mrs $0, MPIDR_EL1 135 ubfx $0, $0, #MPIDR_CORETYPE_SHIFT, #MPIDR_CORETYPE_WIDTH 136 and $0, $0, #MPIDR_CORETYPE_ACC_P 137 #else 138 mov $0, xzr 139 #endif 140 .endmacro 141 142 143 /* 144 * Determines whether the executing core is an E-core. 145 * 146 * @note Clobbers condition flags. 147 * 148 * @param arg0 result register; will be non-zero if executed on an E-core, else 149 * zero if executed on a P-core / non-PE core / non-AMP architectures. 150 */ 151 .macro ARM64_IS_ECORE 152 #if defined(APPLEMONSOON) || HAS_CLUSTER 153 mrs $0, MPIDR_EL1 154 ands $0, $0, #(MPIDR_CORETYPE_MASK << MPIDR_CORETYPE_SHIFT) 155 csinc $0, xzr, xzr, ne 156 #else 157 mov $0, xzr 158 #endif 159 .endmacro 160 161 /* 162 * Reads a system register using the appropriate name for E-cores, P-cores and 163 * non-PE cores. 164 * 165 * @note See also: ARM64_IS_ECORE 166 * 167 * @param arg0 GPR indicating the core type; non-zero if this is an E-core, else zero 168 * @param arg1 destination GPR 169 * @param arg2 system register name to use for E-cores 170 * @param arg3 system register name to use for P-cores, non-PE cores or 171 * non-AMP architectures. 172 */ 173 .macro ARM64_READ_CORE_SYSREG 174 #if defined(APPLEMONSOON) || HAS_CLUSTER 175 cbz $0, 1f 176 // E-core 177 mrs $1, $2 178 b 2f 179 // non-PE core / P-core / non-AMP architecture 180 1: 181 #endif /* defined(APPLEMONSOON) || HAS_CLUSTER */ 182 mrs $1, $3 183 2: 184 .endmacro 185 186 /* 187 * Writes a system register using the appropriate name for E-cores, P-cores and 188 * non-PE cores. 189 * 190 * @note See also: ARM64_IS_ECORE 191 * 192 * @param arg0 GPR indicating the core type; non-zero if this is an E-core, else zero 193 * @param arg1 source GPR 194 * @param arg2 system register name to use for E-cores 195 * @param arg3 system register name to use for P-cores, non-PE cores or 196 * non-AMP architectures. 197 */ 198 .macro ARM64_WRITE_CORE_SYSREG 199 #if defined(APPLEMONSOON) || HAS_CLUSTER 200 cbz $0, 1f 201 // E-core 202 msr $2, $1 203 b 2f 204 // non-PE core / P-core / non-AMP architecture 205 1: 206 #endif /* defined(APPLEMONSOON) || HAS_CLUSTER */ 207 msr $3, $1 208 2: 209 .endmacro 210 211 #endif /* ASSEMBLER */ 212 213 #endif /* ! _PEXPERT_ARM_ARM64_H */ 214