1 /* 2 * Copyright (c) 2007-2023 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 /* CMU_ENDHIST */ 32 /* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or [email protected] 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58 /* 59 * Processor registers for ARM/ARM64 60 */ 61 #ifndef _ARM64_PROC_REG_H_ 62 #define _ARM64_PROC_REG_H_ 63 64 #if defined (__arm64__) 65 #include <pexpert/arm64/board_config.h> 66 #elif defined (__arm__) 67 #include <pexpert/arm/board_config.h> 68 #endif 69 70 /* 71 * Processor registers for ARM 72 */ 73 #if __ARM_42BIT_PA_SPACE__ 74 /* For now, force the issue! */ 75 /* We need more VA space for the identity map to bootstrap the MMU */ 76 #undef __ARM64_PMAP_SUBPAGE_L1__ 77 #endif /* __ARM_42BIT_PA_SPACE__ */ 78 79 /* For arm platforms, create one pset per cluster */ 80 #define MAX_PSETS MAX_CPU_CLUSTERS 81 82 83 /* Thread groups are enabled on all ARM platforms (irrespective of scheduler) */ 84 #define CONFIG_THREAD_GROUPS 1 85 86 #ifdef XNU_KERNEL_PRIVATE 87 88 #if __ARM_VFP__ 89 #define ARM_VFP_DEBUG 0 90 #endif /* __ARM_VFP__ */ 91 92 #endif /* XNU_KERNEL_PRIVATE */ 93 94 /* 95 * FSR registers 96 * 97 * CPSR: Current Program Status Register 98 * SPSR: Saved Program Status Registers 99 * 100 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0 101 * +-----------------------------------------------------------+ 102 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE | 103 * +-----------------------------------------------------------+ 104 */ 105 106 /* 107 * Flags 108 */ 109 #define PSR_NF 0x80000000 /* Negative/Less than */ 110 #define PSR_ZF 0x40000000 /* Zero */ 111 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */ 112 #define PSR_VF 0x10000000 /* Overflow */ 113 114 /* 115 * Modified execution mode flags 116 */ 117 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */ 118 119 /* 120 * CPU mode 121 */ 122 #define PSR_USER_MODE 0x00000010 /* User mode */ 123 124 #define PSR_MODE_MASK 0x0000001F 125 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE) 126 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE) 127 128 #define PSR_USERDFLT PSR_USER_MODE 129 130 #define PSR_BTYPE_SHIFT (10) 131 #define PSR_BTYPE_MASK (0x3 << PSR_BTYPE_SHIFT) 132 133 /* 134 * Cache configuration 135 */ 136 137 #if defined (APPLETYPHOON) 138 139 /* I-Cache */ 140 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 141 142 /* D-Cache */ 143 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 144 145 #elif defined (APPLETWISTER) 146 147 /* I-Cache */ 148 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 149 150 /* D-Cache */ 151 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 152 153 #elif defined (APPLEHURRICANE) 154 155 /* I-Cache */ 156 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 157 158 /* D-Cache */ 159 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 160 161 #elif defined (APPLEMONSOON) 162 163 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */ 164 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 165 166 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */ 167 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 168 169 #elif defined (APPLEVORTEX) 170 171 /* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */ 172 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 173 174 /* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */ 175 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 176 177 #elif defined (APPLELIGHTNING) 178 179 /* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */ 180 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 181 182 /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */ 183 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 184 185 #elif defined (APPLEFIRESTORM) 186 187 /* I-Cache, 256KB for Firestorm, 128KB for Icestorm, 6-way. */ 188 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 189 190 /* D-Cache, 160KB for Firestorm, 8-way. 64KB for Icestorm, 6-way. */ 191 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 192 193 #elif defined (APPLEAVALANCHE) 194 195 /* I-Cache, 192KB for Avalanche, 128KB for Blizzard, 6-way. */ 196 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 197 198 /* D-Cache, 128KB for Avalanche, 8-way. 64KB for Blizzard, 8-way. */ 199 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 200 201 #elif defined (APPLEEVEREST) 202 203 /* I-Cache, 192KB for Everest, 128KB for SawTooth, 6-way. */ 204 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 205 206 /* D-Cache, 128KB for Everest, 8-way. 64KB for SawTooth, 8-way. */ 207 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 208 209 #elif defined (APPLEH16) 210 211 /* I-Cache, 192KB for AppleH16 PCore, 128KB for ECore, 6-way. */ 212 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 213 214 /* D-Cache, 128KB for AppleH16 PCore, 8-way. 64KB for ECore, 8-way. */ 215 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 216 217 #elif defined (VMAPPLE) 218 219 /* I-Cache. */ 220 #define MMU_I_CLINE 6 221 222 /* D-Cache. */ 223 #define MMU_CLINE 6 224 225 #else 226 #error processor not supported 227 #endif 228 229 #define MAX_L2_CLINE_BYTES (1 << MAX_L2_CLINE) 230 231 /* 232 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers 233 */ 234 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */ 235 #define ARM_DBG_VR_ADDRESS_MASK64 0xFFFFFFFFFFFFFFFCull /* BVR & WVR */ 236 237 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */ 238 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */ 239 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */ 240 #define ARM_DBGBCR_TYPE_IVA (0 << 21) 241 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */ 242 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20) 243 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14) 244 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13) 245 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */ 246 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */ 247 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */ 248 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */ 249 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */ 250 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */ 251 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0) 252 253 /* 254 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR) 255 */ 256 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55 257 258 /* ARM Debug registers of interest */ 259 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310) 260 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0) 261 262 /* 263 * Main ID Register (MIDR) 264 * 265 * 31 24 23 20 19 16 15 4 3 0 266 * +-----+-----+------+------+-----+ 267 * | IMP | VAR | ARCH | PNUM | REV | 268 * +-----+-----+------+------+-----+ 269 * 270 * where: 271 * IMP: Implementor code 272 * VAR: Variant number 273 * ARCH: Architecture code 274 * PNUM: Primary part number 275 * REV: Minor revision number 276 */ 277 #define MIDR_REV_SHIFT 0 278 #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT) 279 #define MIDR_VAR_SHIFT 20 280 #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT) 281 282 283 #if __ARM_KERNEL_PROTECT__ 284 /* 285 * __ARM_KERNEL_PROTECT__ is a feature intended to guard against potential 286 * architectural or microarchitectural vulnerabilities that could allow cores to 287 * read/access EL1-only mappings while in EL0 mode. This is achieved by 288 * removing as many mappings as possible when the core transitions to EL0 mode 289 * from EL1 mode, and restoring those mappings when the core transitions to EL1 290 * mode from EL0 mode. 291 * 292 * At the moment, this is achieved through use of ASIDs and TCR_EL1. TCR_EL1 is 293 * used to map and unmap the ordinary kernel mappings, by contracting and 294 * expanding translation zone size for TTBR1 when exiting and entering EL1, 295 * respectively: 296 * 297 * Kernel EL0 Mappings: TTBR1 mappings that must remain mapped while the core is 298 * is in EL0. 299 * Kernel EL1 Mappings: TTBR1 mappings that must be mapped while the core is in 300 * EL1. 301 * 302 * T1SZ_USER: T1SZ_BOOT + 1 303 * TTBR1_EL1_BASE_BOOT: (2^64) - (2^(64 - T1SZ_BOOT) 304 * TTBR1_EL1_BASE_USER: (2^64) - (2^(64 - T1SZ_USER) 305 * TTBR1_EL1_MAX: (2^64) - 1 306 * 307 * When in EL1, we program TCR_EL1 (specifically, TCR_EL1.T1SZ) to give the 308 * the following TTBR1 layout: 309 * 310 * TTBR1_EL1_BASE_BOOT TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 311 * +---------------------------------------------------------+ 312 * | Kernel EL0 Mappings | Kernel EL1 Mappings | 313 * +---------------------------------------------------------+ 314 * 315 * And when in EL0, we program TCR_EL1 to give the following TTBR1 layout: 316 * 317 * TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 318 * +---------------------------------------------------------+ 319 * | Kernel EL0 Mappings | 320 * +---------------------------------------------------------+ 321 * 322 * With the current implementation, both the EL0 and EL1 mappings for the kernel 323 * use otherwise empty translation tables for mapping the exception vectors (so 324 * that we do not need to TLB flush the exception vector address when switching 325 * between EL0 and EL1). The rationale here is that the TLBI would require a 326 * DSB, and DSBs can be extremely expensive. 327 * 328 * Each pmap is given two ASIDs: (n & ~1) as an EL0 ASID, and (n | 1) as an EL1 329 * ASID. The core switches between ASIDs on EL transitions, so that the TLB 330 * does not need to be fully invalidated on an EL transition. 331 * 332 * Most kernel mappings will be marked non-global in this configuration, as 333 * global mappings would be visible to userspace unless we invalidate them on 334 * eret. 335 */ 336 #if XNU_MONITOR 337 /* 338 * Please note that because we indirect through the thread register in order to 339 * locate the kernel, and because we unmap most of the kernel, the security 340 * model of the PPL is undermined by __ARM_KERNEL_PROTECT__, as we rely on 341 * kernel controlled data to direct codeflow in the exception vectors. 342 * 343 * If we want to ship XNU_MONITOR paired with __ARM_KERNEL_PROTECT__, we will 344 * need to find a performant solution to this problem. 345 */ 346 #endif 347 #endif /* __ARM_KERNEL_PROTECT */ 348 349 #if ARM_PARAMETERIZED_PMAP 350 /* 351 * ARM_PARAMETERIZED_PMAP configures the kernel to get the characteristics of 352 * the page tables (number of levels, size of the root allocation) from the 353 * pmap data structure, rather than treating them as compile-time constants. 354 * This allows the pmap code to dynamically adjust how it deals with page 355 * tables. 356 */ 357 #endif /* ARM_PARAMETERIZED_PMAP */ 358 359 #if __ARM_MIXED_PAGE_SIZE__ 360 /* 361 * __ARM_MIXED_PAGE_SIZE__ configures the kernel to support page tables that do 362 * not use the kernel page size. This is primarily meant to support running 363 * 4KB page processes on a 16KB page kernel. 364 * 365 * This only covers support in the pmap/machine dependent layers. Any support 366 * elsewhere in the kernel must be managed separately. 367 */ 368 #if !ARM_PARAMETERIZED_PMAP 369 /* 370 * Page tables that use non-kernel page sizes require us to reprogram TCR based 371 * on the page tables we are switching to. This means that the parameterized 372 * pmap support is required. 373 */ 374 #error __ARM_MIXED_PAGE_SIZE__ requires ARM_PARAMETERIZED_PMAP 375 #endif /* !ARM_PARAMETERIZED_PMAP */ 376 #if __ARM_KERNEL_PROTECT__ 377 /* 378 * Because switching the page size requires updating TCR based on the pmap, and 379 * __ARM_KERNEL_PROTECT__ relies on TCR being programmed with constants, XNU 380 * does not currently support support configurations that use both 381 * __ARM_KERNEL_PROTECT__ and __ARM_MIXED_PAGE_SIZE__. 382 */ 383 #error __ARM_MIXED_PAGE_SIZE__ and __ARM_KERNEL_PROTECT__ are mutually exclusive 384 #endif /* __ARM_KERNEL_PROTECT__ */ 385 #endif /* __ARM_MIXED_PAGE_SIZE__ */ 386 387 /* 388 * 64-bit Program Status Register (PSR64) 389 * 390 * 31 27 23 22 21 20 19 10 9 5 4 0 391 * +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ 392 * |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | 393 * +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ 394 * 395 * where: 396 * NZCV: Comparison flags 397 * PAN: Privileged Access Never 398 * SS: Single step 399 * IL: Illegal state 400 * DAIF: Interrupt masks 401 * M: Mode field 402 */ 403 404 #define PSR64_NZCV_SHIFT 28 405 #define PSR64_NZCV_MASK (0xF << PSR64_NZCV_SHIFT) 406 407 #define PSR64_N_SHIFT 31 408 #define PSR64_N (1 << PSR64_N_SHIFT) 409 410 #define PSR64_Z_SHIFT 30 411 #define PSR64_Z (1 << PSR64_Z_SHIFT) 412 413 #define PSR64_C_SHIFT 29 414 #define PSR64_C (1 << PSR64_C_SHIFT) 415 416 #define PSR64_V_SHIFT 28 417 #define PSR64_V (1 << PSR64_V_SHIFT) 418 419 #define PSR64_TCO_SHIFT 25 420 #define PSR64_TCO (1 << PSR64_TCO_SHIFT) 421 422 #define PSR64_DIT_SHIFT 24 423 #define PSR64_DIT (1 << PSR64_DIT_SHIFT) 424 425 #define PSR64_UAO_SHIFT 23 426 #define PSR64_UAO (1 << PSR64_UAO_SHIFT) 427 428 #define PSR64_PAN_SHIFT 22 429 #define PSR64_PAN (1 << PSR64_PAN_SHIFT) 430 431 #define PSR64_SS_SHIFT 21 432 #define PSR64_SS (1 << PSR64_SS_SHIFT) 433 434 #define PSR64_IL_SHIFT 20 435 #define PSR64_IL (1 << PSR64_IL_SHIFT) 436 437 /* 438 * SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR 439 * I do not want to talk about it! 440 */ 441 #define PSR64_SSBS_SHIFT_32 23 442 #define PSR64_SSBS_SHIFT_64 12 443 #define PSR64_SSBS_32 (1 << PSR64_SSBS_SHIFT_32) 444 #define PSR64_SSBS_64 (1 << PSR64_SSBS_SHIFT_64) 445 446 /* 447 * msr DAIF, Xn and mrs Xn, DAIF transfer into 448 * and out of bits 9:6 449 */ 450 #define DAIF_DEBUG_SHIFT 9 451 #define DAIF_DEBUGF (1 << DAIF_DEBUG_SHIFT) 452 453 #define DAIF_ASYNC_SHIFT 8 454 #define DAIF_ASYNCF (1 << DAIF_ASYNC_SHIFT) 455 456 #define DAIF_IRQF_SHIFT 7 457 #define DAIF_IRQF (1 << DAIF_IRQF_SHIFT) 458 459 #define DAIF_FIQF_SHIFT 6 460 #define DAIF_FIQF (1 << DAIF_FIQF_SHIFT) 461 462 #define DAIF_ALL (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 463 #define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 464 465 #define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF)) 466 467 #if HAS_ARM_FEAT_SSBS2 468 #define PSR64_SSBS_U32_DEFAULT PSR64_SSBS_32 469 #define PSR64_SSBS_U64_DEFAULT PSR64_SSBS_64 470 #define PSR64_SSBS_KRN_DEFAULT PSR64_SSBS_64 471 #else 472 #define PSR64_SSBS_U32_DEFAULT (0) 473 #define PSR64_SSBS_U64_DEFAULT (0) 474 #define PSR64_SSBS_KRN_DEFAULT (0) 475 #endif 476 477 /* 478 * msr DAIFSet, Xn, and msr DAIFClr, Xn transfer 479 * from bits 3:0. 480 */ 481 #define DAIFSC_DEBUGF (1 << 3) 482 #define DAIFSC_ASYNCF (1 << 2) 483 #define DAIFSC_IRQF (1 << 1) 484 #define DAIFSC_FIQF (1 << 0) 485 #define DAIFSC_ALL (DAIFSC_DEBUGF | DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 486 #define DAIFSC_STANDARD_DISABLE (DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 487 #define DAIFSC_NOASYNC (DAIFSC_DEBUGF | DAIFSC_IRQF | DAIFSC_FIQF) 488 489 /* 490 * ARM64_TODO: unify with ARM? 491 */ 492 #define PSR64_CF 0x20000000 /* Carry/Borrow/Extend */ 493 494 #define PSR64_MODE_MASK 0x1F 495 496 #define PSR64_USER_MASK PSR64_NZCV_MASK 497 498 #define PSR64_MODE_USER32_THUMB 0x20 499 500 #define PSR64_MODE_RW_SHIFT 4 501 #define PSR64_MODE_RW_64 0 502 #define PSR64_MODE_RW_32 (0x1 << PSR64_MODE_RW_SHIFT) 503 504 #define PSR64_MODE_EL_SHIFT 2 505 #define PSR64_MODE_EL_MASK (0x3 << PSR64_MODE_EL_SHIFT) 506 #define PSR64_MODE_EL3 (0x3 << PSR64_MODE_EL_SHIFT) 507 #define PSR64_MODE_EL2 (0x2 << PSR64_MODE_EL_SHIFT) 508 #define PSR64_MODE_EL1 (0x1 << PSR64_MODE_EL_SHIFT) 509 #define PSR64_MODE_EL0 0 510 511 #define PSR64_MODE_EL_KERNEL (PSR64_MODE_EL1) 512 513 #define PSR64_MODE_SPX 0x1 514 #define PSR64_MODE_SP0 0 515 516 #define PSR64_USER32_DEFAULT (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U32_DEFAULT) 517 #define PSR64_USER64_DEFAULT (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U64_DEFAULT) 518 #define PSR64_KERNEL_STANDARD (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0 | PSR64_SSBS_KRN_DEFAULT) 519 #if __ARM_PAN_AVAILABLE__ 520 #define PSR64_KERNEL_DEFAULT (PSR64_KERNEL_STANDARD | PSR64_PAN) 521 #else 522 #define PSR64_KERNEL_DEFAULT PSR64_KERNEL_STANDARD 523 #endif 524 525 #define PSR64_IS_KERNEL(x) ((x & PSR64_MODE_EL_MASK) > PSR64_MODE_EL0) 526 #define PSR64_IS_USER(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0) 527 528 #define PSR64_IS_USER32(x) (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32)) 529 #define PSR64_IS_USER64(x) (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32)) 530 531 532 533 /* 534 * System Control Register (SCTLR) 535 */ 536 537 #if HAS_ARM_FEAT_SME 538 // 60 EnTP2 Enable TPIDR2_EL0 at EL0 539 #define SCTLR_OTHER (1ULL << 60) 540 #else 541 #define SCTLR_OTHER (0) 542 #endif 543 544 #define SCTLR_DSSBS (1ULL << 44) 545 546 547 #define SCTLR_EXTRA (0) 548 549 550 #define SCTLR_RESERVED ((3ULL << 28) | (1ULL << 20)) 551 #if defined(HAS_APPLE_PAC) 552 553 // 31 PACIA_ENABLED AddPACIA and AuthIA functions enabled 554 #define SCTLR_PACIA_ENABLED_SHIFT 31 555 #define SCTLR_PACIA_ENABLED (1ULL << SCTLR_PACIA_ENABLED_SHIFT) 556 // 30 PACIB_ENABLED AddPACIB and AuthIB functions enabled 557 #define SCTLR_PACIB_ENABLED (1ULL << 30) 558 // 29:28 RES1 11 559 // 27 PACDA_ENABLED AddPACDA and AuthDA functions enabled 560 #define SCTLR_PACDA_ENABLED (1ULL << 27) 561 // 13 PACDB_ENABLED AddPACDB and AuthDB functions enabled 562 #define SCTLR_PACDB_ENABLED (1ULL << 13) 563 564 #define SCTLR_PAC_KEYS_ENABLED (SCTLR_PACIA_ENABLED | SCTLR_PACIB_ENABLED | SCTLR_PACDA_ENABLED | SCTLR_PACDB_ENABLED) 565 #endif /* defined(HAS_APPLE_PAC) */ 566 567 // 36 BT1 PACIxSP acts as a BTI C landing pad rather than BTI JC at EL1 568 #define SCTLR_BT1_ENABLED (1ULL << 36) 569 570 // 35 BT0 PACIxSP acts as a BTI C landing pad rather than BTI JC at EL0 571 #define SCTLR_BT0_ENABLED (1ULL << 35) 572 573 // 26 UCI User Cache Instructions 574 #define SCTLR_UCI_ENABLED (1ULL << 26) 575 576 // 25 EE Exception Endianness 577 #define SCTLR_EE_BIG_ENDIAN (1ULL << 25) 578 579 // 24 E0E EL0 Endianness 580 #define SCTLR_E0E_BIG_ENDIAN (1ULL << 24) 581 582 // 23 SPAN Set PAN 583 #define SCTLR_PAN_UNCHANGED (1ULL << 23) 584 585 // 22 EIS Taking an exception is a context synchronization event 586 #define SCTLR_EIS (1ULL << 22) 587 588 // 21 RES0 0 589 // 20 RES1 1 590 591 // 19 WXN Writeable implies eXecute Never 592 #define SCTLR_WXN_ENABLED (1ULL << 19) 593 594 // 18 nTWE Not trap WFE from EL0 595 #define SCTLR_nTWE_WFE_ENABLED (1ULL << 18) 596 597 // 17 RES0 0 598 599 // 16 nTWI Not trap WFI from EL0 600 #define SCTRL_nTWI_WFI_ENABLED (1ULL << 16) 601 602 // 15 UCT User Cache Type register (CTR_EL0) 603 #define SCTLR_UCT_ENABLED (1ULL << 15) 604 605 // 14 DZE User Data Cache Zero (DC ZVA) 606 #define SCTLR_DZE_ENABLED (1ULL << 14) 607 608 // 12 I Instruction cache enable 609 #define SCTLR_I_ENABLED (1ULL << 12) 610 611 // 11 EOS Exception return is a context synchronization event 612 #define SCTLR_EOS (1ULL << 11) 613 614 // 10 EnRCTX EL0 Access to FEAT_SPECRES speculation restriction instructions 615 #define SCTLR_EnRCTX (1ULL << 10) 616 617 // 9 UMA User Mask Access 618 #define SCTLR_UMA_ENABLED (1ULL << 9) 619 620 // 8 SED SETEND Disable 621 #define SCTLR_SED_DISABLED (1ULL << 8) 622 623 // 7 ITD IT Disable 624 #define SCTLR_ITD_DISABLED (1ULL << 7) 625 626 // 6 RES0 0 627 628 // 5 CP15BEN CP15 Barrier ENable 629 #define SCTLR_CP15BEN_ENABLED (1ULL << 5) 630 631 // 4 SA0 Stack Alignment check for EL0 632 #define SCTLR_SA0_ENABLED (1ULL << 4) 633 634 // 3 SA Stack Alignment check 635 #define SCTLR_SA_ENABLED (1ULL << 3) 636 637 // 2 C Cache enable 638 #define SCTLR_C_ENABLED (1ULL << 2) 639 640 // 1 A Alignment check 641 #define SCTLR_A_ENABLED (1ULL << 1) 642 643 // 0 M MMU enable 644 #define SCTLR_M_ENABLED (1ULL << 0) 645 646 #if __ARM_ARCH_8_5__ 647 #define SCTLR_CSEH_DEFAULT (0) 648 #define SCTLR_DSSBS_DEFAULT SCTLR_DSSBS 649 #else 650 #define SCTLR_CSEH_DEFAULT (SCTLR_EIS | SCTLR_EOS) 651 #define SCTLR_DSSBS_DEFAULT (0) 652 #endif 653 654 #if HAS_APPLE_PAC 655 #define SCTLR_PAC_KEYS_DEFAULT SCTLR_PAC_KEYS_ENABLED 656 #else /* !HAS_APPLE_PAC */ 657 #define SCTLR_PAC_KEYS_DEFAULT 0 658 #endif 659 660 #if BTI_ENFORCED 661 /* In the kernel, we want PACIxSP to behave only as a BTI C */ 662 #define SCTLR_BT_DEFAULT SCTLR_BT1_ENABLED 663 #else 664 #define SCTLR_BT_DEFAULT 0 665 #endif /* BTI_ENFORCED */ 666 667 #define SCTLR_EL1_DEFAULT \ 668 (SCTLR_RESERVED | SCTLR_UCI_ENABLED | SCTLR_nTWE_WFE_ENABLED | SCTLR_DZE_ENABLED | \ 669 SCTLR_I_ENABLED | SCTLR_SED_DISABLED | SCTLR_CP15BEN_ENABLED | SCTLR_BT_DEFAULT | \ 670 SCTLR_SA0_ENABLED | SCTLR_SA_ENABLED | SCTLR_C_ENABLED | SCTLR_M_ENABLED | \ 671 SCTLR_CSEH_DEFAULT | SCTLR_DSSBS_DEFAULT | SCTLR_PAC_KEYS_DEFAULT | SCTLR_OTHER) 672 673 /* 674 * Coprocessor Access Control Register (CPACR) 675 * 676 * 31 28 27 22 21 20 19 0 677 * +---+---+------+------+--------------------+ 678 * |000|TTA|000000| FPEN |00000000000000000000| 679 * +---+---+------+------+--------------------+ 680 * 681 * where: 682 * TTA: Trace trap 683 * FPEN: Floating point enable 684 */ 685 #define CPACR_TTA_SHIFT 28 686 #define CPACR_TTA (1 << CPACR_TTA_SHIFT) 687 688 #if HAS_ARM_FEAT_SME 689 #define CPACR_SMEN_SHIFT 24 690 #define CPACR_SMEN_MASK (0x3 << CPACR_SMEN_SHIFT) 691 #define CPACR_SMEN_EL0_TRAP (0x1 << CPACR_SMEN_SHIFT) 692 #define CPACR_SMEN_ENABLE (0x3 << CPACR_SMEN_SHIFT) 693 #endif /* HAS_ARM_FEAT_SME */ 694 695 #define CPACR_FPEN_SHIFT 20 696 #define CPACR_FPEN_EL0_TRAP (0x1 << CPACR_FPEN_SHIFT) 697 #define CPACR_FPEN_ENABLE (0x3 << CPACR_FPEN_SHIFT) 698 699 #if HAS_ARM_FEAT_SME 700 #define CPACR_ZEN_SHIFT 16 701 #define CPACR_ZEN_MASK (0x3 << CPACR_ZEN_SHIFT) 702 #define CPACR_ZEN_EL0_TRAP (0x1 << CPACR_ZEN_SHIFT) 703 #define CPACR_ZEN_ENABLE (0x3 << CPACR_ZEN_SHIFT) 704 #endif /* HAS_ARM_FEAT_SME */ 705 706 /* 707 * FPSR: Floating Point Status Register 708 * 709 * 31 30 29 28 27 26 7 6 4 3 2 1 0 710 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 711 * | N| Z| C| V|QC|0000000000000000000|IDC|00|IXC|UFC|OFC|DZC|IOC| 712 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 713 */ 714 715 #define FPSR_N_SHIFT 31 716 #define FPSR_Z_SHIFT 30 717 #define FPSR_C_SHIFT 29 718 #define FPSR_V_SHIFT 28 719 #define FPSR_QC_SHIFT 27 720 #define FPSR_IDC_SHIFT 7 721 #define FPSR_IXC_SHIFT 4 722 #define FPSR_UFC_SHIFT 3 723 #define FPSR_OFC_SHIFT 2 724 #define FPSR_DZC_SHIFT 1 725 #define FPSR_IOC_SHIFT 0 726 #define FPSR_N (1 << FPSR_N_SHIFT) 727 #define FPSR_Z (1 << FPSR_Z_SHIFT) 728 #define FPSR_C (1 << FPSR_C_SHIFT) 729 #define FPSR_V (1 << FPSR_V_SHIFT) 730 #define FPSR_QC (1 << FPSR_QC_SHIFT) 731 #define FPSR_IDC (1 << FPSR_IDC_SHIFT) 732 #define FPSR_IXC (1 << FPSR_IXC_SHIFT) 733 #define FPSR_UFC (1 << FPSR_UFC_SHIFT) 734 #define FPSR_OFC (1 << FPSR_OFC_SHIFT) 735 #define FPSR_DZC (1 << FPSR_DZC_SHIFT) 736 #define FPSR_IOC (1 << FPSR_IOC_SHIFT) 737 738 /* 739 * A mask for all for all of the bits that are not RAZ for FPSR; this 740 * is primarily for converting between a 32-bit view of NEON state 741 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 742 */ 743 #define FPSR_MASK \ 744 (FPSR_N | FPSR_Z | FPSR_C | FPSR_V | FPSR_QC | FPSR_IDC | FPSR_IXC | \ 745 FPSR_UFC | FPSR_OFC | FPSR_DZC | FPSR_IOC) 746 747 /* 748 * FPCR: Floating Point Control Register 749 * 750 * 31 26 25 24 23 21 19 18 15 14 12 11 10 9 8 7 0 751 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 752 * |00000|AHP|DN|FZ|RMODE|STRIDE| 0|LEN|IDE|00|IXE|UFE|OFE|DZE|IOE|00000000| 753 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 754 */ 755 756 #define FPCR_AHP_SHIFT 26 757 #define FPCR_DN_SHIFT 25 758 #define FPCR_FZ_SHIFT 24 759 #define FPCR_RMODE_SHIFT 22 760 #define FPCR_STRIDE_SHIFT 20 761 #define FPCR_LEN_SHIFT 16 762 #define FPCR_IDE_SHIFT 15 763 #define FPCR_IXE_SHIFT 12 764 #define FPCR_UFE_SHIFT 11 765 #define FPCR_OFE_SHIFT 10 766 #define FPCR_DZE_SHIFT 9 767 #define FPCR_IOE_SHIFT 8 768 #define FPCR_AHP (1 << FPCR_AHP_SHIFT) 769 #define FPCR_DN (1 << FPCR_DN_SHIFT) 770 #define FPCR_FZ (1 << FPCR_FZ_SHIFT) 771 #define FPCR_RMODE (0x3 << FPCR_RMODE_SHIFT) 772 #define FPCR_STRIDE (0x3 << FPCR_STRIDE_SHIFT) 773 #define FPCR_LEN (0x7 << FPCR_LEN_SHIFT) 774 #define FPCR_IDE (1 << FPCR_IDE_SHIFT) 775 #define FPCR_IXE (1 << FPCR_IXE_SHIFT) 776 #define FPCR_UFE (1 << FPCR_UFE_SHIFT) 777 #define FPCR_OFE (1 << FPCR_OFE_SHIFT) 778 #define FPCR_DZE (1 << FPCR_DZE_SHIFT) 779 #define FPCR_IOE (1 << FPCR_IOE_SHIFT) 780 #define FPCR_DEFAULT (0) 781 #define FPCR_DEFAULT_32 (FPCR_DN|FPCR_FZ) 782 783 /* 784 * A mask for all for all of the bits that are not RAZ for FPCR; this 785 * is primarily for converting between a 32-bit view of NEON state 786 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 787 */ 788 #define FPCR_MASK \ 789 (FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE | FPCR_STRIDE | FPCR_LEN | \ 790 FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE) 791 792 /* 793 * Translation Control Register (TCR) 794 * 795 * Legacy: 796 * 797 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 798 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 799 * | zero |TBI1|TBI0|AS|z| IPS |z|TG1| SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ |z|TG0| SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 800 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 801 * 802 * Current (with 16KB granule support): 803 * 804 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 805 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 806 * | zero |TBI1|TBI0|AS|z| IPS | TG1 | SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ | TG0 | SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 807 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 808 * 809 * TBI1: Top Byte Ignored for TTBR1 region 810 * TBI0: Top Byte Ignored for TTBR0 region 811 * AS: ASID Size 812 * IPS: Physical Address Size limit 813 * TG1: Granule Size for TTBR1 region 814 * SH1: Shareability for TTBR1 region 815 * ORGN1: Outer Cacheability for TTBR1 region 816 * IRGN1: Inner Cacheability for TTBR1 region 817 * EPD1: Translation table walk disable for TTBR1 818 * A1: ASID selection from TTBR1 enable 819 * T1SZ: Virtual address size for TTBR1 820 * TG0: Granule Size for TTBR0 region 821 * SH0: Shareability for TTBR0 region 822 * ORGN0: Outer Cacheability for TTBR0 region 823 * IRGN0: Inner Cacheability for TTBR0 region 824 * T0SZ: Virtual address size for TTBR0 825 */ 826 827 #define TCR_T0SZ_SHIFT 0ULL 828 #define TCR_TSZ_BITS 6ULL 829 #define TCR_TSZ_MASK ((1ULL << TCR_TSZ_BITS) - 1ULL) 830 831 #define TCR_IRGN0_SHIFT 8ULL 832 #define TCR_IRGN0_DISABLED (0ULL << TCR_IRGN0_SHIFT) 833 #define TCR_IRGN0_WRITEBACK (1ULL << TCR_IRGN0_SHIFT) 834 #define TCR_IRGN0_WRITETHRU (2ULL << TCR_IRGN0_SHIFT) 835 #define TCR_IRGN0_WRITEBACKNO (3ULL << TCR_IRGN0_SHIFT) 836 837 #define TCR_ORGN0_SHIFT 10ULL 838 #define TCR_ORGN0_DISABLED (0ULL << TCR_ORGN0_SHIFT) 839 #define TCR_ORGN0_WRITEBACK (1ULL << TCR_ORGN0_SHIFT) 840 #define TCR_ORGN0_WRITETHRU (2ULL << TCR_ORGN0_SHIFT) 841 #define TCR_ORGN0_WRITEBACKNO (3ULL << TCR_ORGN0_SHIFT) 842 843 #define TCR_SH0_SHIFT 12ULL 844 #define TCR_SH0_NONE (0ULL << TCR_SH0_SHIFT) 845 #define TCR_SH0_OUTER (2ULL << TCR_SH0_SHIFT) 846 #define TCR_SH0_INNER (3ULL << TCR_SH0_SHIFT) 847 848 #define TCR_TG0_GRANULE_SHIFT (14ULL) 849 #define TCR_TG0_GRANULE_BITS (2ULL) 850 #define TCR_TG0_GRANULE_MASK ((1ULL << TCR_TG0_GRANULE_BITS) - 1ULL) 851 852 #define TCR_TG0_GRANULE_4KB (0ULL << TCR_TG0_GRANULE_SHIFT) 853 #define TCR_TG0_GRANULE_64KB (1ULL << TCR_TG0_GRANULE_SHIFT) 854 #define TCR_TG0_GRANULE_16KB (2ULL << TCR_TG0_GRANULE_SHIFT) 855 856 #if __ARM_16K_PG__ 857 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_16KB) 858 #else 859 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_4KB) 860 #endif 861 862 #define TCR_T1SZ_SHIFT 16ULL 863 864 #define TCR_A1_ASID1 (1ULL << 22ULL) 865 #define TCR_EPD1_TTBR1_DISABLED (1ULL << 23ULL) 866 867 #define TCR_IRGN1_SHIFT 24ULL 868 #define TCR_IRGN1_DISABLED (0ULL << TCR_IRGN1_SHIFT) 869 #define TCR_IRGN1_WRITEBACK (1ULL << TCR_IRGN1_SHIFT) 870 #define TCR_IRGN1_WRITETHRU (2ULL << TCR_IRGN1_SHIFT) 871 #define TCR_IRGN1_WRITEBACKNO (3ULL << TCR_IRGN1_SHIFT) 872 873 #define TCR_ORGN1_SHIFT 26ULL 874 #define TCR_ORGN1_DISABLED (0ULL << TCR_ORGN1_SHIFT) 875 #define TCR_ORGN1_WRITEBACK (1ULL << TCR_ORGN1_SHIFT) 876 #define TCR_ORGN1_WRITETHRU (2ULL << TCR_ORGN1_SHIFT) 877 #define TCR_ORGN1_WRITEBACKNO (3ULL << TCR_ORGN1_SHIFT) 878 879 #define TCR_SH1_SHIFT 28ULL 880 #define TCR_SH1_NONE (0ULL << TCR_SH1_SHIFT) 881 #define TCR_SH1_OUTER (2ULL << TCR_SH1_SHIFT) 882 #define TCR_SH1_INNER (3ULL << TCR_SH1_SHIFT) 883 884 #define TCR_TG1_GRANULE_SHIFT 30ULL 885 #define TCR_TG1_GRANULE_BITS (2ULL) 886 #define TCR_TG1_GRANULE_MASK ((1ULL << TCR_TG1_GRANULE_BITS) - 1ULL) 887 888 #define TCR_TG1_GRANULE_16KB (1ULL << TCR_TG1_GRANULE_SHIFT) 889 #define TCR_TG1_GRANULE_4KB (2ULL << TCR_TG1_GRANULE_SHIFT) 890 #define TCR_TG1_GRANULE_64KB (3ULL << TCR_TG1_GRANULE_SHIFT) 891 892 #if __ARM_16K_PG__ 893 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_16KB) 894 #else 895 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_4KB) 896 #endif 897 898 #define TCR_IPS_SHIFT 32ULL 899 #define TCR_IPS_BITS 3ULL 900 #define TCR_IPS_MASK ((1ULL << TCR_IPS_BITS) - 1ULL) 901 #define TCR_IPS_32BITS (0ULL << TCR_IPS_SHIFT) 902 #define TCR_IPS_36BITS (1ULL << TCR_IPS_SHIFT) 903 #define TCR_IPS_40BITS (2ULL << TCR_IPS_SHIFT) 904 #define TCR_IPS_42BITS (3ULL << TCR_IPS_SHIFT) 905 #define TCR_IPS_44BITS (4ULL << TCR_IPS_SHIFT) 906 #define TCR_IPS_48BITS (5ULL << TCR_IPS_SHIFT) 907 908 #define TCR_AS_16BIT_ASID (1ULL << 36) 909 #define TCR_TBI0_TOPBYTE_IGNORED (1ULL << 37) 910 #define TCR_TBI1_TOPBYTE_IGNORED (1ULL << 38) 911 #define TCR_TBID0_TBI_DATA_ONLY (1ULL << 51) 912 #define TCR_TBID1_TBI_DATA_ONLY (1ULL << 52) 913 914 #if defined(HAS_APPLE_PAC) 915 #define TCR_TBID0_ENABLE TCR_TBID0_TBI_DATA_ONLY 916 #define TCR_TBID1_ENABLE TCR_TBID1_TBI_DATA_ONLY 917 #else 918 #define TCR_TBID0_ENABLE 0 919 #define TCR_TBID1_ENABLE 0 920 #endif 921 922 #define TCR_E0PD0_BIT (1ULL << 55) 923 #define TCR_E0PD1_BIT (1ULL << 56) 924 925 #if defined(HAS_E0PD) 926 #define TCR_E0PD_VALUE (TCR_E0PD1_BIT) 927 #else 928 #define TCR_E0PD_VALUE 0 929 #endif 930 931 932 #define TCR_EL1_EXTRA 0 933 934 935 /* 936 * Multiprocessor Affinity Register (MPIDR_EL1) 937 * 938 * +64-----------------------------31+30+29-25+24+23-16+15-8+7--0+ 939 * |000000000000000000000000000000001| U|00000|MT| Aff2|Aff1|Aff0| 940 * +---------------------------------+--+-----+--+-----+----+----+ 941 * 942 * where 943 * U: Uniprocessor 944 * MT: Multi-threading at lowest affinity level 945 * Aff2: "1" - PCORE, "0" - ECORE 946 * Aff1: Cluster ID 947 * Aff0: CPU ID 948 */ 949 #define MPIDR_AFF0_SHIFT 0 950 #define MPIDR_AFF0_WIDTH 8 951 #define MPIDR_AFF0_MASK (((1 << MPIDR_AFF0_WIDTH) - 1) << MPIDR_AFF0_SHIFT) 952 #define MPIDR_AFF1_SHIFT 8 953 #define MPIDR_AFF1_WIDTH 8 954 #define MPIDR_AFF1_MASK (((1 << MPIDR_AFF1_WIDTH) - 1) << MPIDR_AFF1_SHIFT) 955 #define MPIDR_AFF2_SHIFT 16 956 #define MPIDR_AFF2_WIDTH 8 957 #define MPIDR_AFF2_MASK (((1 << MPIDR_AFF2_WIDTH) - 1) << MPIDR_AFF2_SHIFT) 958 959 /* 960 * TXSZ indicates the size of the range a TTBR covers. Currently, 961 * we support the following: 962 * 963 * 4KB pages, full page L1: 39 bit range. 964 * 4KB pages, sub-page L1: 38 bit range. 965 * 16KB pages, full page L1: 47 bit range. 966 * 16KB pages, sub-page L1: 39 bit range. 967 * 16KB pages, two level page tables: 36 bit range. 968 */ 969 #if __ARM_KERNEL_PROTECT__ 970 /* 971 * If we are configured to use __ARM_KERNEL_PROTECT__, the first half of the 972 * address space is used for the mappings that will remain in place when in EL0. 973 * As a result, 1 bit less of address space is available to the rest of the 974 * the kernel. 975 */ 976 #endif /* __ARM_KERNEL_PROTECT__ */ 977 #ifdef __ARM_16K_PG__ 978 #if __ARM64_PMAP_SUBPAGE_L1__ 979 #define T0SZ_BOOT 25ULL 980 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 981 #define T0SZ_BOOT 17ULL 982 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 983 #else /* __ARM_16K_PG__ */ 984 #if __ARM64_PMAP_SUBPAGE_L1__ 985 #define T0SZ_BOOT 26ULL 986 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 987 #define T0SZ_BOOT 25ULL 988 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 989 #endif /* __ARM_16K_PG__ */ 990 991 #if defined(APPLE_ARM64_ARCH_FAMILY) 992 /* T0SZ must be the same as T1SZ */ 993 #define T1SZ_BOOT T0SZ_BOOT 994 #else /* defined(APPLE_ARM64_ARCH_FAMILY) */ 995 #ifdef __ARM_16K_PG__ 996 #if __ARM64_PMAP_SUBPAGE_L1__ 997 #define T1SZ_BOOT 25ULL 998 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 999 #define T1SZ_BOOT 17ULL 1000 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 1001 #else /* __ARM_16K_PG__ */ 1002 #if __ARM64_PMAP_SUBPAGE_L1__ 1003 #define T1SZ_BOOT 26ULL 1004 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1005 #define T1SZ_BOOT 25ULL 1006 #endif /*__ARM64_PMAP_SUBPAGE_L1__*/ 1007 #endif /* __ARM_16K_PG__ */ 1008 #endif /* defined(APPLE_ARM64_ARCH_FAMILY) */ 1009 1010 #if __ARM_42BIT_PA_SPACE__ 1011 #define TCR_IPS_VALUE TCR_IPS_42BITS 1012 #else /* !__ARM_42BIT_PA_SPACE__ */ 1013 #define TCR_IPS_VALUE TCR_IPS_40BITS 1014 #endif /* !__ARM_42BIT_PA_SPACE__ */ 1015 1016 #if CONFIG_KERNEL_TBI 1017 #define TCR_EL1_DTBI (TCR_TBI1_TOPBYTE_IGNORED | TCR_TBID1_ENABLE) 1018 #else /* CONFIG_KERNEL_TBI */ 1019 #define TCR_EL1_DTBI 0 1020 #endif /* CONFIG_KERNEL_TBI */ 1021 1022 #if HAS_16BIT_ASID 1023 #define TCR_EL1_ASID TCR_AS_16BIT_ASID 1024 #else /* HAS_16BIT_ASID */ 1025 #define TCR_EL1_ASID 0 1026 #endif /* HAS_16BIT_ASID */ 1027 1028 #define TCR_EL1_BASE \ 1029 (TCR_IPS_VALUE | TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK | \ 1030 TCR_IRGN0_WRITEBACK | (T0SZ_BOOT << TCR_T0SZ_SHIFT) | \ 1031 TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | \ 1032 TCR_IRGN1_WRITEBACK | (TCR_TG1_GRANULE_SIZE) | \ 1033 TCR_TBI0_TOPBYTE_IGNORED | (TCR_TBID0_ENABLE) | TCR_E0PD_VALUE | \ 1034 TCR_EL1_DTBI | TCR_EL1_ASID | TCR_EL1_EXTRA) 1035 1036 #if __ARM_KERNEL_PROTECT__ 1037 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1038 #define T1SZ_USER (T1SZ_BOOT + 1) 1039 #define TCR_EL1_USER (TCR_EL1_BASE | (T1SZ_USER << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1040 #else 1041 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1042 #endif /* __ARM_KERNEL_PROTECT__ */ 1043 1044 #define TCR_EL1_4KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_4KB)) 1045 #define TCR_EL1_16KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_16KB)) 1046 1047 1048 1049 1050 /* 1051 * Monitor Debug System Control Register (MDSCR) 1052 */ 1053 1054 #define MDSCR_TFO_SHIFT 31 1055 #define MDSCR_TFO (1ULL << MDSCR_TFO_SHIFT) 1056 #define MDSCR_RXFULL_SHIFT 30 1057 #define MDSCR_RXFULL (1ULL << MDSCR_RXFULL_SHIFT) 1058 #define MDSCR_TXFULL_SHIFT 29 1059 #define MDSCR_TXFULL (1ULL << MDSCR_TXFULL_SHIFT) 1060 #define MDSCR_RXO_SHIFT 27 1061 #define MDSCR_RXO (1ULL << MDSCR_RXO_SHIFT) 1062 #define MDSCR_TXU_SHIFT 26 1063 #define MDSCR_TXU (1ULL << MDSCR_TXU_SHIFT) 1064 #define MDSCR_INTDIS_SHIFT 22 1065 #define MDSCR_INTDIS_MASK (0x2U << MDSCR_INTDIS_SHIFT) 1066 #define MDSCR_TDA_SHIFT 21 1067 #define MDSCR_TDA (1ULL << MDSCR_TDA_SHIFT) 1068 #define MDSCR_SC2_SHIFT 19 1069 #define MDSCR_SC2 (1ULL << MDSCR_SC2_SHIFT) 1070 #define MDSCR_MDE_SHIFT 15 1071 #define MDSCR_MDE (1ULL << MDSCR_MDE_SHIFT) 1072 #define MDSCR_HDE_SHIFT 14 1073 #define MDSCR_HDE (1ULL << MDSCR_HDE_SHIFT) 1074 #define MDSCR_KDE_SHIFT 13 1075 #define MDSCR_KDE (1ULL << MDSCR_KDE_SHIFT) 1076 #define MDSCR_TDCC_SHIFT 12 1077 #define MDSCR_TDCC (1ULL << MDSCR_TDCC_SHIFT) 1078 #define MDSCR_ERR_SHIFT 6 1079 #define MDSCR_ERR (1ULL << MDSCR_ERR_SHIFT) 1080 #define MDSCR_SS_SHIFT 0 1081 #define MDSCR_SS (1ULL << MDSCR_SS_SHIFT) 1082 1083 /* 1084 * Translation Table Base Register (TTBR) 1085 * 1086 * 63 48 47 x x-1 0 1087 * +--------+------------------+------+ 1088 * | ASID | Base Address | zero | 1089 * +--------+------------------+------+ 1090 * 1091 */ 1092 #define TTBR_ASID_SHIFT 48 1093 #define TTBR_ASID_MASK 0xffff000000000000 1094 1095 #define TTBR_BADDR_MASK 0x0000ffffffffffff 1096 1097 /* 1098 * Memory Attribute Indirection Register 1099 * 1100 * 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 1101 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1102 * | Attr7 | Attr6 | Attr5 | Attr4 | Attr3 | Attr2 | Attr1 | Attr0 | 1103 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1104 * 1105 */ 1106 1107 #define MAIR_ATTR_SHIFT(x) (8*(x)) 1108 1109 /* Strongly ordered or device memory attributes */ 1110 #define MAIR_OUTER_STRONGLY_ORDERED 0x0 1111 #define MAIR_OUTER_DEVICE 0x0 1112 1113 #define MAIR_INNER_STRONGLY_ORDERED 0x0 1114 #define MAIR_INNER_DEVICE 0x4 1115 1116 /* Normal memory attributes */ 1117 #define MAIR_OUTER_NON_CACHEABLE 0x40 1118 #define MAIR_OUTER_WRITE_THROUGH 0x80 1119 #define MAIR_OUTER_WRITE_BACK 0xc0 1120 1121 #define MAIR_INNER_NON_CACHEABLE 0x4 1122 #define MAIR_INNER_WRITE_THROUGH 0x8 1123 #define MAIR_INNER_WRITE_BACK 0xc 1124 1125 /* Allocate policy for cacheable memory */ 1126 #define MAIR_OUTER_WRITE_ALLOCATE 0x10 1127 #define MAIR_OUTER_READ_ALLOCATE 0x20 1128 1129 #define MAIR_INNER_WRITE_ALLOCATE 0x1 1130 #define MAIR_INNER_READ_ALLOCATE 0x2 1131 1132 /* Memory Atribute Encoding */ 1133 1134 /* 1135 * Device memory types: 1136 * G (gathering): multiple reads/writes can be combined 1137 * R (reordering): reads or writes may reach device out of program order 1138 * E (early-acknowledge): writes may return immediately (e.g. PCIe posted writes) 1139 */ 1140 #if HAS_FEAT_XS 1141 1142 #define MAIR_DISABLE_XS 0x00 /* Device Memory, nGnRnE (strongly ordered), XS=1 */ 1143 #define MAIR_DISABLE 0x01 /* Device Memory, nGnRnE (strongly ordered), XS=0 */ 1144 #define MAIR_POSTED_COMBINED_REORDERED_XS 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=1 */ 1145 #define MAIR_POSTED_COMBINED_REORDERED 0x0D /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=0 */ 1146 #define MAIR_WRITECOMB 0x40 /* Normal Memory, Non-Cacheable, XS=0 */ 1147 #define MAIR_WRITETHRU 0xA0 /* Normal Memory, Write-through, XS=0 */ 1148 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Write-back, XS=0 */ 1149 1150 1151 /* 1152 * Memory Attribute Index. If these values change, please also update the pmap 1153 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1154 */ 1155 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1156 #define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1157 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1158 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1159 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory), XS = 0 */ 1160 #define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1161 #define CACHE_ATTRINDX_DISABLE_XS 0x5 /* no cache, no buffer (device memory), XS = 1 */ 1162 /** 1163 * Posted mappings use XS by default, and on newer Apple SoCs there is no fabric-level distinction 1164 * between early-ack and non-early-ack, so just alias POSTED to DISABLE_XS to save a MAIR index. 1165 */ 1166 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE_XS 1167 #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE /* no need for device-nGRE on newer SoCs, fallback to nGnRnE */ 1168 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x6 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=0 */ 1169 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED_XS 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=1 */ 1170 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1171 #define CACHE_ATTRINDX_N_INDICES (8ULL) 1172 1173 #else 1174 1175 #define MAIR_DISABLE 0x00 /* Device Memory, nGnRnE (strongly ordered) */ 1176 #define MAIR_POSTED 0x04 /* Device Memory, nGnRE (strongly ordered, posted writes) */ 1177 #define MAIR_POSTED_REORDERED 0x08 /* Device Memory, nGRE (reorderable, posted writes) */ 1178 #define MAIR_POSTED_COMBINED_REORDERED 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes) */ 1179 #define MAIR_WRITECOMB 0x44 /* Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable */ 1180 #define MAIR_WRITETHRU 0xBB /* Normal Memory, Outer Write-through, Inner Write-through */ 1181 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Outer Write-back, Inner Write-back */ 1182 1183 /* 1184 * Memory Attribute Index. If these values change, please also update the pmap 1185 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1186 */ 1187 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1188 #define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1189 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1190 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1191 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory) */ 1192 #define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1193 #define CACHE_ATTRINDX_POSTED 0x5 /* no cache, no buffer, posted writes (device memory) */ 1194 #define CACHE_ATTRINDX_POSTED_REORDERED 0x6 /* no cache, reorderable access, posted writes (device memory) */ 1195 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory) */ 1196 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1197 #define CACHE_ATTRINDX_N_INDICES (8ULL) 1198 1199 #endif /* HAS_FEAT_XS */ 1200 1201 #if HAS_UCNORMAL_MEM 1202 #define CACHE_ATTRINDX_RT CACHE_ATTRINDX_WRITECOMB 1203 #else 1204 #define CACHE_ATTRINDX_RT CACHE_ATTRINDX_DISABLE 1205 #endif /* HAS_UCNORMAL_MEM */ 1206 1207 1208 1209 /* 1210 * Access protection bit values (TTEs and PTEs), stage 1 1211 * 1212 * Bit 1 controls access type (1=RO, 0=RW), bit 0 controls user (1=access, 0=no access) 1213 */ 1214 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */ 1215 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */ 1216 #define AP_RONA 0x2 /* priv=read-only, user=no-access */ 1217 #define AP_RORO 0x3 /* priv=read-only, user=read-only */ 1218 #define AP_MASK 0x3 /* mask to find ap bits */ 1219 1220 /* 1221 * Shareability attributes 1222 */ 1223 #define SH_NONE 0x0 /* Non shareable */ 1224 #define SH_NONE 0x0 /* Device shareable */ 1225 #define SH_DEVICE 0x2 /* Normal memory Inner non shareable - Outer non shareable */ 1226 #define SH_OUTER_MEMORY 0x2 /* Normal memory Inner shareable - Outer shareable */ 1227 #define SH_INNER_MEMORY 0x3 /* Normal memory Inner shareable - Outer non shareable */ 1228 1229 1230 /* 1231 * ARM Page Granule 1232 */ 1233 #ifdef __ARM_16K_PG__ 1234 #define ARM_PGSHIFT 14 1235 #else 1236 #define ARM_PGSHIFT 12 1237 #endif 1238 #define ARM_PGBYTES (1 << ARM_PGSHIFT) 1239 #define ARM_PGMASK (ARM_PGBYTES-1) 1240 1241 /* 1242 * L0 Translation table 1243 * 1244 * 4KB granule size: 1245 * Each translation table is 4KB 1246 * 512 64-bit entries of 512GB (2^39) of address space. 1247 * Covers 256TB (2^48) of address space. 1248 * 1249 * 16KB granule size: 1250 * Each translation table is 16KB 1251 * 2 64-bit entries of 128TB (2^47) of address space. 1252 * Covers 256TB (2^48) of address space. 1253 */ 1254 1255 /* 16K L0 */ 1256 #define ARM_16K_TT_L0_SIZE 0x0000800000000000ULL /* size of area covered by a tte */ 1257 #define ARM_16K_TT_L0_OFFMASK 0x00007fffffffffffULL /* offset within an L0 entry */ 1258 #define ARM_16K_TT_L0_SHIFT 47 /* page descriptor shift */ 1259 #define ARM_16K_TT_L0_INDEX_MASK 0x0000800000000000ULL /* mask for getting index in L0 table from virtual address */ 1260 1261 /* 4K L0 */ 1262 #define ARM_4K_TT_L0_SIZE 0x0000008000000000ULL /* size of area covered by a tte */ 1263 #define ARM_4K_TT_L0_OFFMASK 0x0000007fffffffffULL /* offset within an L0 entry */ 1264 #define ARM_4K_TT_L0_SHIFT 39 /* page descriptor shift */ 1265 #define ARM_4K_TT_L0_INDEX_MASK 0x0000ff8000000000ULL /* mask for getting index in L0 table from virtual address */ 1266 1267 /* 1268 * L1 Translation table 1269 * 1270 * 4KB granule size: 1271 * Each translation table is 4KB 1272 * 512 64-bit entries of 1GB (2^30) of address space. 1273 * Covers 512GB (2^39) of address space. 1274 * 1275 * 16KB granule size: 1276 * Each translation table is 16KB 1277 * 2048 64-bit entries of 64GB (2^36) of address space. 1278 * Covers 128TB (2^47) of address space. 1279 */ 1280 1281 /* 16K L1 */ 1282 #define ARM_16K_TT_L1_SIZE 0x0000001000000000ULL /* size of area covered by a tte */ 1283 #define ARM_16K_TT_L1_OFFMASK 0x0000000fffffffffULL /* offset within an L1 entry */ 1284 #define ARM_16K_TT_L1_SHIFT 36 /* page descriptor shift */ 1285 #if __ARM64_PMAP_SUBPAGE_L1__ && __ARM_16K_PG__ 1286 /* This config supports 512GB per TTBR. */ 1287 #define ARM_16K_TT_L1_INDEX_MASK 0x0000007000000000ULL /* mask for getting index into L1 table from virtual address */ 1288 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1289 #define ARM_16K_TT_L1_INDEX_MASK 0x00007ff000000000ULL /* mask for getting index into L1 table from virtual address */ 1290 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1291 1292 /* 4K L1 */ 1293 #define ARM_4K_TT_L1_SIZE 0x0000000040000000ULL /* size of area covered by a tte */ 1294 #define ARM_4K_TT_L1_OFFMASK 0x000000003fffffffULL /* offset within an L1 entry */ 1295 #define ARM_4K_TT_L1_SHIFT 30 /* page descriptor shift */ 1296 #if __ARM64_PMAP_SUBPAGE_L1__ && !__ARM_16K_PG__ 1297 /* This config supports 256GB per TTBR. */ 1298 #define ARM_4K_TT_L1_INDEX_MASK 0x0000003fc0000000ULL /* mask for getting index into L1 table from virtual address */ 1299 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1300 /* IPA[38:30] mask for getting index into L1 table from virtual address */ 1301 #define ARM_4K_TT_L1_INDEX_MASK 0x0000007fc0000000ULL 1302 #if __ARM_42BIT_PA_SPACE__ 1303 /* IPA[39:30] mask for getting index into L1 concatenated table from virtual address */ 1304 #define ARM_4K_TT_L1_40_BIT_CONCATENATED_INDEX_MASK 0x000000ffc0000000ULL 1305 #endif /* __ARM_42BIT_PA_SPACE__ */ 1306 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1307 1308 /* some sugar for getting pointers to page tables and entries */ 1309 1310 #define L1_TABLE_INDEX(va) (((va) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT) 1311 #define L2_TABLE_INDEX(va) (((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT) 1312 #define L3_TABLE_INDEX(va) (((va) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT) 1313 1314 #define L2_TABLE_VA(tte) ((tt_entry_t*) phystokv((*(tte)) & ARM_TTE_TABLE_MASK)) 1315 #define L3_TABLE_VA(tte2) ((pt_entry_t*) phystokv((*(tte2)) & ARM_TTE_TABLE_MASK)) 1316 1317 /* 1318 * L2 Translation table 1319 * 1320 * 4KB granule size: 1321 * Each translation table is 4KB 1322 * 512 64-bit entries of 2MB (2^21) of address space. 1323 * Covers 1GB (2^30) of address space. 1324 * 1325 * 16KB granule size: 1326 * Each translation table is 16KB 1327 * 2048 64-bit entries of 32MB (2^25) of address space. 1328 * Covers 64GB (2^36) of address space. 1329 */ 1330 1331 /* 16K L2 */ 1332 #define ARM_16K_TT_L2_SIZE 0x0000000002000000ULL /* size of area covered by a tte */ 1333 #define ARM_16K_TT_L2_OFFMASK 0x0000000001ffffffULL /* offset within an L2 entry */ 1334 #define ARM_16K_TT_L2_SHIFT 25 /* page descriptor shift */ 1335 #define ARM_16K_TT_L2_INDEX_MASK 0x0000000ffe000000ULL /* mask for getting index in L2 table from virtual address */ 1336 1337 /* 4K L2 */ 1338 #define ARM_4K_TT_L2_SIZE 0x0000000000200000ULL /* size of area covered by a tte */ 1339 #define ARM_4K_TT_L2_OFFMASK 0x00000000001fffffULL /* offset within an L2 entry */ 1340 #define ARM_4K_TT_L2_SHIFT 21 /* page descriptor shift */ 1341 #define ARM_4K_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */ 1342 1343 /* 1344 * L3 Translation table 1345 * 1346 * 4KB granule size: 1347 * Each translation table is 4KB 1348 * 512 64-bit entries of 4KB (2^12) of address space. 1349 * Covers 2MB (2^21) of address space. 1350 * 1351 * 16KB granule size: 1352 * Each translation table is 16KB 1353 * 2048 64-bit entries of 16KB (2^14) of address space. 1354 * Covers 32MB (2^25) of address space. 1355 */ 1356 1357 /* 16K L3 */ 1358 #define ARM_16K_TT_L3_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1359 #define ARM_16K_TT_L3_OFFMASK 0x0000000000003fffULL /* offset within L3 PTE */ 1360 #define ARM_16K_TT_L3_SHIFT 14 /* page descriptor shift */ 1361 #define ARM_16K_TT_L3_INDEX_MASK 0x0000000001ffc000ULL /* mask for page descriptor index */ 1362 1363 /* 4K L3 */ 1364 #define ARM_4K_TT_L3_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1365 #define ARM_4K_TT_L3_OFFMASK 0x0000000000000fffULL /* offset within L3 PTE */ 1366 #define ARM_4K_TT_L3_SHIFT 12 /* page descriptor shift */ 1367 #define ARM_4K_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */ 1368 1369 #ifdef __ARM_16K_PG__ 1370 1371 /* Native L0 defines */ 1372 #define ARM_TT_L0_SIZE ARM_16K_TT_L0_SIZE 1373 #define ARM_TT_L0_OFFMASK ARM_16K_TT_L0_OFFMASK 1374 #define ARM_TT_L0_SHIFT ARM_16K_TT_L0_SHIFT 1375 #define ARM_TT_L0_INDEX_MASK ARM_16K_TT_L0_INDEX_MASK 1376 1377 /* Native L1 defines */ 1378 #define ARM_TT_L1_SIZE ARM_16K_TT_L1_SIZE 1379 #define ARM_TT_L1_OFFMASK ARM_16K_TT_L1_OFFMASK 1380 #define ARM_TT_L1_SHIFT ARM_16K_TT_L1_SHIFT 1381 #define ARM_TT_L1_INDEX_MASK ARM_16K_TT_L1_INDEX_MASK 1382 1383 /* Native L2 defines */ 1384 #define ARM_TT_L2_SIZE ARM_16K_TT_L2_SIZE 1385 #define ARM_TT_L2_OFFMASK ARM_16K_TT_L2_OFFMASK 1386 #define ARM_TT_L2_SHIFT ARM_16K_TT_L2_SHIFT 1387 #define ARM_TT_L2_INDEX_MASK ARM_16K_TT_L2_INDEX_MASK 1388 1389 /* Native L3 defines */ 1390 #define ARM_TT_L3_SIZE ARM_16K_TT_L3_SIZE 1391 #define ARM_TT_L3_OFFMASK ARM_16K_TT_L3_OFFMASK 1392 #define ARM_TT_L3_SHIFT ARM_16K_TT_L3_SHIFT 1393 #define ARM_TT_L3_INDEX_MASK ARM_16K_TT_L3_INDEX_MASK 1394 1395 #else /* !__ARM_16K_PG__ */ 1396 1397 /* Native L0 defines */ 1398 #define ARM_TT_L0_SIZE ARM_4K_TT_L0_SIZE 1399 #define ARM_TT_L0_OFFMASK ARM_4K_TT_L0_OFFMASK 1400 #define ARM_TT_L0_SHIFT ARM_4K_TT_L0_SHIFT 1401 #define ARM_TT_L0_INDEX_MASK ARM_4K_TT_L0_INDEX_MASK 1402 1403 /* Native L1 defines */ 1404 #define ARM_TT_L1_SIZE ARM_4K_TT_L1_SIZE 1405 #define ARM_TT_L1_OFFMASK ARM_4K_TT_L1_OFFMASK 1406 #define ARM_TT_L1_SHIFT ARM_4K_TT_L1_SHIFT 1407 #define ARM_TT_L1_INDEX_MASK ARM_4K_TT_L1_INDEX_MASK 1408 1409 /* Native L2 defines */ 1410 #define ARM_TT_L2_SIZE ARM_4K_TT_L2_SIZE 1411 #define ARM_TT_L2_OFFMASK ARM_4K_TT_L2_OFFMASK 1412 #define ARM_TT_L2_SHIFT ARM_4K_TT_L2_SHIFT 1413 #define ARM_TT_L2_INDEX_MASK ARM_4K_TT_L2_INDEX_MASK 1414 1415 /* Native L3 defines */ 1416 #define ARM_TT_L3_SIZE ARM_4K_TT_L3_SIZE 1417 #define ARM_TT_L3_OFFMASK ARM_4K_TT_L3_OFFMASK 1418 #define ARM_TT_L3_SHIFT ARM_4K_TT_L3_SHIFT 1419 #define ARM_TT_L3_INDEX_MASK ARM_4K_TT_L3_INDEX_MASK 1420 1421 #endif /* !__ARM_16K_PG__ */ 1422 1423 /* 1424 * Convenience definitions for: 1425 * ARM_TT_LEAF: The last level of the configured page table format. 1426 * ARM_TT_TWIG: The second to last level of the configured page table format. 1427 * ARM_TT_ROOT: The first level of the configured page table format. 1428 * 1429 * My apologies to any botanists who may be reading this. 1430 */ 1431 #define ARM_TT_LEAF_SIZE ARM_TT_L3_SIZE 1432 #define ARM_TT_LEAF_OFFMASK ARM_TT_L3_OFFMASK 1433 #define ARM_TT_LEAF_SHIFT ARM_TT_L3_SHIFT 1434 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L3_INDEX_MASK 1435 1436 #define ARM_TT_TWIG_SIZE ARM_TT_L2_SIZE 1437 #define ARM_TT_TWIG_OFFMASK ARM_TT_L2_OFFMASK 1438 #define ARM_TT_TWIG_SHIFT ARM_TT_L2_SHIFT 1439 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L2_INDEX_MASK 1440 1441 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE 1442 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK 1443 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT 1444 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK 1445 1446 /* 1447 * 4KB granule size: 1448 * 1449 * Level 0 Translation Table Entry 1450 * 1451 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1452 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1453 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1454 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1455 * 1456 * Level 1 Translation Table Entry 1457 * 1458 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1459 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1460 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 1461 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1462 * 1463 * Level 1 Translation Block Entry 1464 * 1465 * 63 59 58 55 54 53 52 51 48 47 30 29 12 11 10 9 8 7 6 5 4 2 1 0 1466 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1467 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:30] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1468 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1469 * 1470 * Level 2 Translation Table Entry 1471 * 1472 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1473 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1474 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 1475 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1476 * 1477 * Level 2 Translation Block Entry 1478 * 1479 * 63 59 58 55 54 53 52 51 48 47 21 20 12 11 10 9 8 7 6 5 4 2 1 0 1480 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1481 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:21] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1482 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1483 * 1484 * 16KB granule size: 1485 * 1486 * Level 0 Translation Table Entry 1487 * 1488 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1489 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1490 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1491 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1492 * 1493 * Level 1 Translation Table Entry 1494 * 1495 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1496 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1497 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 1498 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1499 * 1500 * Level 2 Translation Table Entry 1501 * 1502 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1503 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1504 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 1505 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1506 * 1507 * Level 2 Translation Block Entry 1508 * 1509 * 63 59 58 55 54 53 52 51 48 47 25 24 12 11 10 9 8 7 6 5 4 2 1 0 1510 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1511 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:25] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1512 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1513 * 1514 * where: 1515 * nG: notGlobal bit 1516 * SH: Shareability field 1517 * AP: access protection 1518 * XN: eXecute Never bit 1519 * PXN: Privilege eXecute Never bit 1520 * NS: Non-Secure bit 1521 * HINT: 16 entry continuguous output hint 1522 * AttrIdx: Memory Attribute Index 1523 */ 1524 1525 #define TTE_SHIFT 3 /* shift width of a tte (sizeof(tte) == (1 << TTE_SHIFT)) */ 1526 #ifdef __ARM_16K_PG__ 1527 #define TTE_PGENTRIES (16384 >> TTE_SHIFT) /* number of ttes per page */ 1528 #else 1529 #define TTE_PGENTRIES (4096 >> TTE_SHIFT) /* number of ttes per page */ 1530 #endif 1531 1532 #define ARM_TTE_MAX (TTE_PGENTRIES) 1533 1534 #define ARM_TTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */ 1535 #define ARM_TTE_TYPE_FAULT 0x0000000000000000ULL /* unasigned - invalid entry */ 1536 1537 #define ARM_TTE_VALID 0x0000000000000001ULL /* valid entry */ 1538 1539 #define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */ 1540 #define ARM_TTE_TYPE_TABLE 0x0000000000000002ULL /* page table type */ 1541 #define ARM_TTE_TYPE_BLOCK 0x0000000000000000ULL /* block entry type */ 1542 #define ARM_TTE_TYPE_L3BLOCK 0x0000000000000002ULL 1543 1544 #ifdef __ARM_16K_PG__ 1545 /* 1546 * Note that L0/L1 block entries are disallowed for the 16KB granule size; what 1547 * are we doing with these? 1548 */ 1549 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 16KB L3 TTE entry */ 1550 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 128TB section */ 1551 #define ARM_TTE_BLOCK_L1_MASK 0x0000fff000000000ULL /* mask to extract phys address from L1 block entry */ 1552 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 64GB section */ 1553 #define ARM_TTE_BLOCK_L2_MASK 0x0000fffffe000000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 1554 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 32MB section */ 1555 #else 1556 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 4KB L3 TTE entry */ 1557 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 2048GB section */ 1558 #define ARM_TTE_BLOCK_L1_MASK 0x0000ffffc0000000ULL /* mask to extract phys address from L1 block entry */ 1559 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 1GB section */ 1560 #define ARM_TTE_BLOCK_L2_MASK 0x0000ffffffe00000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 1561 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 2MB section */ 1562 #endif 1563 1564 #define ARM_TTE_BLOCK_APSHIFT 6 1565 #define ARM_TTE_BLOCK_AP(x) ((x)<<ARM_TTE_BLOCK_APSHIFT) /* access protection */ 1566 #define ARM_TTE_BLOCK_APMASK (0x3 << ARM_TTE_BLOCK_APSHIFT) 1567 1568 #define ARM_TTE_BLOCK_ATTRINDX(x) ((x) << 2) /* memory attributes index */ 1569 #define ARM_TTE_BLOCK_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */ 1570 1571 #define ARM_TTE_BLOCK_SH(x) ((x) << 8) /* access shared */ 1572 #define ARM_TTE_BLOCK_SHMASK (0x3ULL << 8) /* mask access shared */ 1573 1574 #define ARM_TTE_BLOCK_AF 0x0000000000000400ULL /* value for access */ 1575 #define ARM_TTE_BLOCK_AFMASK 0x0000000000000400ULL /* access mask */ 1576 1577 #define ARM_TTE_BLOCK_NG 0x0000000000000800ULL /* value for a global mapping */ 1578 #define ARM_TTE_BLOCK_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 1579 1580 #define ARM_TTE_BLOCK_NS 0x0000000000000020ULL /* value for a secure mapping */ 1581 #define ARM_TTE_BLOCK_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 1582 1583 #define ARM_TTE_BLOCK_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 1584 #define ARM_TTE_BLOCK_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 1585 1586 #define ARM_TTE_BLOCK_NX 0x0040000000000000ULL /* value for no execute */ 1587 #define ARM_TTE_BLOCK_NXMASK 0x0040000000000000ULL /* no execute mask */ 1588 1589 #define ARM_TTE_BLOCK_WIRED 0x0400000000000000ULL /* value for software wired bit */ 1590 #define ARM_TTE_BLOCK_WIREDMASK 0x0400000000000000ULL /* software wired mask */ 1591 1592 #define ARM_TTE_BLOCK_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 1593 #define ARM_TTE_BLOCK_WRITEABLEMASK 0x0800000000000000ULL /* software writeable mask */ 1594 1595 #define ARM_TTE_TABLE_MASK 0x0000fffffffff000ULL /* mask for extracting pointer to next table (works at any level) */ 1596 1597 #define ARM_TTE_TABLE_APSHIFT 61 1598 #define ARM_TTE_TABLE_AP_NO_EFFECT 0x0ULL 1599 #define ARM_TTE_TABLE_AP_USER_NA 0x1ULL 1600 #define ARM_TTE_TABLE_AP_RO 0x2ULL 1601 #define ARM_TTE_TABLE_AP_KERN_RO 0x3ULL 1602 #define ARM_TTE_TABLE_AP(x) ((x) << ARM_TTE_TABLE_APSHIFT) /* access protection */ 1603 1604 #define ARM_TTE_TABLE_NS 0x8000000000000020ULL /* value for a secure mapping */ 1605 #define ARM_TTE_TABLE_NS_MASK 0x8000000000000020ULL /* notSecure mapping mask */ 1606 1607 #define ARM_TTE_TABLE_XN 0x1000000000000000ULL /* value for no execute */ 1608 #define ARM_TTE_TABLE_XNMASK 0x1000000000000000ULL /* no execute mask */ 1609 1610 #define ARM_TTE_TABLE_PXN 0x0800000000000000ULL /* value for privilege no execute bit */ 1611 #define ARM_TTE_TABLE_PXNMASK 0x0800000000000000ULL /* privilege execute mask */ 1612 1613 #if __ARM_KERNEL_PROTECT__ 1614 #define ARM_TTE_BOOT_BLOCK \ 1615 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 1616 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF | ARM_TTE_BLOCK_NG) 1617 #else /* __ARM_KERNEL_PROTECT__ */ 1618 #define ARM_TTE_BOOT_BLOCK \ 1619 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 1620 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF) 1621 #endif /* __ARM_KERNEL_PROTECT__ */ 1622 1623 #define ARM_TTE_BOOT_TABLE (ARM_TTE_TYPE_TABLE | ARM_TTE_VALID ) 1624 /* 1625 * L3 Translation table 1626 * 1627 * 4KB granule size: 1628 * Each translation table is 4KB 1629 * 512 64-bit entries of 4KB (2^12) of address space. 1630 * Covers 2MB (2^21) of address space. 1631 * 1632 * 16KB granule size: 1633 * Each translation table is 16KB 1634 * 2048 64-bit entries of 16KB (2^14) of address space. 1635 * Covers 32MB (2^25) of address space. 1636 */ 1637 1638 #ifdef __ARM_16K_PG__ 1639 #define ARM_PTE_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1640 #define ARM_PTE_OFFMASK 0x0000000000003fffULL /* offset within pte area */ 1641 #define ARM_PTE_SHIFT 14 /* page descriptor shift */ 1642 #define ARM_PTE_MASK 0x0000ffffffffc000ULL /* mask for output address in PTE */ 1643 #else 1644 #define ARM_PTE_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1645 #define ARM_PTE_OFFMASK 0x0000000000000fffULL /* offset within pte area */ 1646 #define ARM_PTE_SHIFT 12 /* page descriptor shift */ 1647 #define ARM_PTE_MASK 0x0000fffffffff000ULL /* mask for output address in PTE */ 1648 #endif 1649 1650 #define ARM_TTE_PA_MASK 0x0000fffffffff000ULL 1651 1652 /* 1653 * L3 Page table entries 1654 * 1655 * The following page table entry types are possible: 1656 * 1657 * fault page entry 1658 * 63 2 0 1659 * +------------------------------+--+ 1660 * | ignored |00| 1661 * +------------------------------+--+ 1662 * 1663 * 1664 * 63 59 58 55 54 53 52 51 50 47 48 12 11 10 9 8 7 6 5 4 2 1 0 1665 * +-----+------+--+---+----+---+--+----+----------------------+--+--+----+----+--+-------+-+-+ 1666 * | ign |sw use|XN|PXN|HINT|DBM|GP|zero| OutputAddress[47:12] |nG|AF| SH | AP |NS|AttrIdx|1|V| 1667 * +-----+------+--+---+----+---+--+----+----------------------+--+--+----+----+--+-------+-+-+ 1668 * 1669 * where: 1670 * nG: notGlobal bit 1671 * SH: Shareability field 1672 * AP: access protection 1673 * XN: eXecute Never bit 1674 * PXN: Privilege eXecute Never bit 1675 * NS: Non-Secure bit 1676 * HINT: 16 entry continuguous output hint 1677 * DBM: Dirty Bit Modifier 1678 * GP: Guraded Page 1679 * AttrIdx: Memory Attribute Index 1680 */ 1681 1682 #define PTE_SHIFT 3 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */ 1683 #ifdef __ARM_16K_PG__ 1684 #define PTE_PGENTRIES (16384 >> PTE_SHIFT) /* number of ptes per page */ 1685 #else 1686 #define PTE_PGENTRIES (4096 >> PTE_SHIFT) /* number of ptes per page */ 1687 #endif 1688 1689 #define ARM_PTE_EMPTY 0x0000000000000000ULL /* unassigned - invalid entry */ 1690 1691 /* markers for (invalid) PTE for a page sent to compressor */ 1692 #define ARM_PTE_COMPRESSED 0x8000000000000000ULL /* compressed... */ 1693 #define ARM_PTE_COMPRESSED_ALT 0x4000000000000000ULL /* ... and was "alt_acct" */ 1694 #define ARM_PTE_COMPRESSED_MASK 0xC000000000000000ULL 1695 1696 #define ARM_PTE_TYPE 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */ 1697 #define ARM_PTE_TYPE_VALID 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */ 1698 #define ARM_PTE_TYPE_FAULT 0x0000000000000000ULL /* invalid L3 entry */ 1699 #define ARM_PTE_TYPE_MASK 0x0000000000000002ULL /* mask to get pte type */ 1700 1701 /* This mask works for both 16K and 4K pages because bits 12-13 will be zero in 16K pages */ 1702 #define ARM_PTE_PAGE_MASK 0x0000FFFFFFFFF000ULL /* output address mask for page */ 1703 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for the output address in the entry */ 1704 1705 #define ARM_PTE_AP(x) ((x) << 6) /* access protections */ 1706 #define ARM_PTE_APMASK (0x3ULL << 6) /* mask access protections */ 1707 #define ARM_PTE_EXTRACT_AP(x) (((x) >> 6) & 0x3ULL) /* extract access protections from PTE */ 1708 1709 #define ARM_PTE_ATTRINDX(x) ((x) << 2) /* memory attributes index */ 1710 #define ARM_PTE_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */ 1711 #define ARM_PTE_EXTRACT_ATTRINDX(x) (((x) >> 2) & 0x7ULL) /* extract memory attributes index */ 1712 1713 #define ARM_PTE_SH(x) ((x) << 8) /* access shared */ 1714 #define ARM_PTE_SHMASK (0x3ULL << 8) /* mask access shared */ 1715 1716 #define ARM_PTE_AF 0x0000000000000400ULL /* value for access */ 1717 #define ARM_PTE_AFMASK 0x0000000000000400ULL /* access mask */ 1718 1719 #define ARM_PTE_NG 0x0000000000000800ULL /* value for a global mapping */ 1720 #define ARM_PTE_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 1721 1722 #define ARM_PTE_NS 0x0000000000000020ULL /* value for a secure mapping */ 1723 #define ARM_PTE_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 1724 1725 #define ARM_PTE_HINT 0x0010000000000000ULL /* value for contiguous entries hint */ 1726 #define ARM_PTE_HINT_MASK 0x0010000000000000ULL /* mask for contiguous entries hint */ 1727 1728 #define ARM_PTE_GP 0x0004000000000000ULL /* value marking a guarded page */ 1729 #define ARM_PTE_GP_MASK 0x0004000000000000ULL /* mask for a guarded page mark */ 1730 1731 #if __ARM_16K_PG__ 1732 #define ARM_PTE_HINT_ENTRIES 128ULL /* number of entries the hint covers */ 1733 #define ARM_PTE_HINT_ENTRIES_SHIFT 7ULL /* shift to construct the number of entries */ 1734 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFE00000ULL /* mask to extract the starting hint address */ 1735 #define ARM_PTE_HINT_ADDR_SHIFT 21 /* shift for the hint address */ 1736 #define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFE00000ULL /* mask to extract the starting hint address */ 1737 #else 1738 #define ARM_PTE_HINT_ENTRIES 16ULL /* number of entries the hint covers */ 1739 #define ARM_PTE_HINT_ENTRIES_SHIFT 4ULL /* shift to construct the number of entries */ 1740 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFFF0000ULL /* mask to extract the starting hint address */ 1741 #define ARM_PTE_HINT_ADDR_SHIFT 16 /* shift for the hint address */ 1742 #define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFFF0000ULL /* mask to extract the starting hint address */ 1743 #endif 1744 1745 #define ARM_PTE_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 1746 #define ARM_PTE_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 1747 1748 #define ARM_PTE_NX 0x0040000000000000ULL /* value for no execute bit */ 1749 #define ARM_PTE_NXMASK 0x0040000000000000ULL /* no execute mask */ 1750 1751 #define ARM_PTE_XMASK (ARM_PTE_PNXMASK | ARM_PTE_NXMASK) 1752 1753 #define ARM_PTE_WIRED 0x0400000000000000ULL /* value for software wired bit */ 1754 #define ARM_PTE_WIRED_MASK 0x0400000000000000ULL /* software wired mask */ 1755 1756 #define ARM_PTE_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 1757 #define ARM_PTE_WRITEABLE_MASK 0x0800000000000000ULL /* software writeable mask */ 1758 1759 #define ARM_PTE_BOOT_PAGE_BASE \ 1760 (ARM_PTE_TYPE_VALID | ARM_PTE_SH(SH_OUTER_MEMORY) | \ 1761 ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_PTE_AF) 1762 1763 #if __ARM_KERNEL_PROTECT__ 1764 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE | ARM_PTE_NG) 1765 #else /* __ARM_KERNEL_PROTECT__ */ 1766 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE) 1767 #endif /* __ARM_KERNEL_PROTECT__ */ 1768 1769 /* 1770 * TLBI appers to only deal in 4KB page addresses, so give 1771 * it an explicit shift of 12. 1772 */ 1773 #define TLBI_ADDR_SHIFT (0) 1774 #define TLBI_ADDR_SIZE (44) 1775 #define TLBI_ADDR_MASK ((1ULL << TLBI_ADDR_SIZE) - 1) 1776 #define TLBI_ASID_SHIFT (48) 1777 #define TLBI_ASID_SIZE (16) 1778 #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1)) 1779 1780 #define RTLBI_ADDR_SIZE (37) 1781 #define RTLBI_ADDR_MASK ((1ULL << RTLBI_ADDR_SIZE) - 1) 1782 #define RTLBI_ADDR_SHIFT ARM_TT_L3_SHIFT 1783 #define RTLBI_TG(_page_shift_) ((uint64_t)((((_page_shift_) - 12) >> 1) + 1) << 46) 1784 #define RTLBI_SCALE_SHIFT (44) 1785 #define RTLBI_NUM_SHIFT (39) 1786 1787 /* 1788 * RCTX instruction operand fields. 1789 */ 1790 #define RCTX_EL_SHIFT (24) 1791 #define RCTX_EL_SIZE (2) 1792 #define RCTX_EL_MASK (((1ULL << RCTX_EL_SIZE) - 1) << RCTX_EL_SHIFT) 1793 #define RCTX_EL(x) ((x << RCTX_EL_SHIFT) & RCTX_EL_MASK) 1794 #define RCTX_ASID_SHIFT (0) 1795 #define RCTX_ASID_SIZE (16) 1796 #define RCTX_ASID_MASK (((1ULL << RCTX_ASID_SIZE) - 1) << RCTX_ASID_SHIFT) 1797 #define RCTX_ASID(x) ((x << RCTX_ASID_SHIFT) & RCTX_ASID_MASK) 1798 1799 /* 1800 * Exception Syndrome Register 1801 * 1802 * 63 56 55 32 31 26 25 24 0 1803 * +------+------+------+--+------------------+ 1804 * | RES0 | ISS2 | EC |IL| ISS | 1805 * +------+------+------+--+------------------+ 1806 * 1807 * RES0 - Reserved bits. 1808 * ISS2 - Instruction Specific Syndrome 2. 1809 * EC - Exception Class 1810 * IL - Instruction Length 1811 * ISS - Instruction Specific Syndrome 1812 * 1813 * Note: The ISS can have many forms. These are defined separately below. 1814 */ 1815 1816 #define ESR_EC_SHIFT 26 1817 #define ESR_EC_MASK (0x3FULL << ESR_EC_SHIFT) 1818 #define ESR_EC(x) ((x & ESR_EC_MASK) >> ESR_EC_SHIFT) 1819 1820 #define ESR_IL_SHIFT 25 1821 #define ESR_IL (1 << ESR_IL_SHIFT) 1822 1823 #define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL)) 1824 1825 #define ESR_ISS_MASK 0x01FFFFFF 1826 #define ESR_ISS(x) (x & ESR_ISS_MASK) 1827 1828 1829 #ifdef __ASSEMBLER__ 1830 /* Define only the classes we need to test in the exception vectors. */ 1831 #define ESR_EC_UNCATEGORIZED 0x00 1832 #define ESR_EC_BTI_FAIL 0x0D 1833 #define ESR_EC_PAC_FAIL 0x1C 1834 #define ESR_EC_IABORT_EL1 0x21 1835 #define ESR_EC_DABORT_EL1 0x25 1836 #define ESR_EC_SP_ALIGN 0x26 1837 #define ESR_EC_BRK_AARCH64 0x3C 1838 #else 1839 typedef enum { 1840 ESR_EC_UNCATEGORIZED = 0x00, 1841 ESR_EC_WFI_WFE = 0x01, 1842 ESR_EC_MCR_MRC_CP15_TRAP = 0x03, 1843 ESR_EC_MCRR_MRRC_CP15_TRAP = 0x04, 1844 ESR_EC_MCR_MRC_CP14_TRAP = 0x05, 1845 ESR_EC_LDC_STC_CP14_TRAP = 0x06, 1846 ESR_EC_TRAP_SIMD_FP = 0x07, 1847 ESR_EC_PTRAUTH_INSTR_TRAP = 0x09, 1848 ESR_EC_MCRR_MRRC_CP14_TRAP = 0x0c, 1849 ESR_EC_BTI_FAIL = 0x0d, 1850 ESR_EC_ILLEGAL_INSTR_SET = 0x0e, 1851 ESR_EC_SVC_32 = 0x11, 1852 ESR_EC_HVC_32 = 0x12, 1853 ESR_EC_SVC_64 = 0x15, 1854 ESR_EC_HVC_64 = 0x16, 1855 ESR_EC_MSR_TRAP = 0x18, 1856 #if __has_feature(ptrauth_calls) 1857 ESR_EC_PAC_FAIL = 0x1C, 1858 #endif /* __has_feature(ptrauth_calls) */ 1859 #if HAS_ARM_FEAT_SME 1860 ESR_EC_SME = 0x1D, 1861 #endif 1862 ESR_EC_IABORT_EL0 = 0x20, 1863 ESR_EC_IABORT_EL1 = 0x21, 1864 ESR_EC_PC_ALIGN = 0x22, 1865 ESR_EC_DABORT_EL0 = 0x24, 1866 ESR_EC_DABORT_EL1 = 0x25, 1867 ESR_EC_SP_ALIGN = 0x26, 1868 ESR_EC_FLOATING_POINT_32 = 0x28, 1869 ESR_EC_FLOATING_POINT_64 = 0x2C, 1870 ESR_EC_SERROR_INTERRUPT = 0x2F, 1871 ESR_EC_BKPT_REG_MATCH_EL0 = 0x30, // Breakpoint Debug event taken to the EL from a lower EL. 1872 ESR_EC_BKPT_REG_MATCH_EL1 = 0x31, // Breakpoint Debug event taken to the EL from the EL. 1873 ESR_EC_SW_STEP_DEBUG_EL0 = 0x32, // Software Step Debug event taken to the EL from a lower EL. 1874 ESR_EC_SW_STEP_DEBUG_EL1 = 0x33, // Software Step Debug event taken to the EL from the EL. 1875 ESR_EC_WATCHPT_MATCH_EL0 = 0x34, // Watchpoint Debug event taken to the EL from a lower EL. 1876 ESR_EC_WATCHPT_MATCH_EL1 = 0x35, // Watchpoint Debug event taken to the EL from the EL. 1877 ESR_EC_BKPT_AARCH32 = 0x38, 1878 ESR_EC_BRK_AARCH64 = 0x3C, 1879 } esr_exception_class_t; 1880 1881 typedef enum { 1882 FSC_TRANSLATION_FAULT_L0 = 0x04, 1883 FSC_TRANSLATION_FAULT_L1 = 0x05, 1884 FSC_TRANSLATION_FAULT_L2 = 0x06, 1885 FSC_TRANSLATION_FAULT_L3 = 0x07, 1886 FSC_ACCESS_FLAG_FAULT_L1 = 0x09, 1887 FSC_ACCESS_FLAG_FAULT_L2 = 0x0A, 1888 FSC_ACCESS_FLAG_FAULT_L3 = 0x0B, 1889 FSC_PERMISSION_FAULT_L1 = 0x0D, 1890 FSC_PERMISSION_FAULT_L2 = 0x0E, 1891 FSC_PERMISSION_FAULT_L3 = 0x0F, 1892 FSC_SYNC_EXT_ABORT = 0x10, 1893 FSC_SYNC_EXT_ABORT_TT_L1 = 0x15, 1894 FSC_SYNC_EXT_ABORT_TT_L2 = 0x16, 1895 FSC_SYNC_EXT_ABORT_TT_L3 = 0x17, 1896 FSC_SYNC_PARITY = 0x18, 1897 FSC_ASYNC_PARITY = 0x19, 1898 FSC_SYNC_PARITY_TT_L1 = 0x1D, 1899 FSC_SYNC_PARITY_TT_L2 = 0x1E, 1900 FSC_SYNC_PARITY_TT_L3 = 0x1F, 1901 FSC_ALIGNMENT_FAULT = 0x21, 1902 FSC_DEBUG_FAULT = 0x22, 1903 } fault_status_t; 1904 #endif /* ASSEMBLER */ 1905 1906 /* 1907 * HVC event 1908 * 24 16 15 0 1909 * +---------+-----+ 1910 * |000000000| IMM | 1911 * +---------+-----+ 1912 * 1913 * where: 1914 * IMM: Immediate value 1915 */ 1916 1917 #define ISS_HVC_IMM_MASK 0xffff 1918 #define ISS_HVC_IMM(x) ((x) & ISS_HVC_IMM_MASK) 1919 1920 /* 1921 * Software step debug event ISS (EL1) 1922 * 24 23 6 5 0 1923 * +---+-----------------+--+------+ 1924 * |ISV|00000000000000000|EX| IFSC | 1925 * +---+-----------------+--+------+ 1926 * 1927 * where: 1928 * ISV: Instruction syndrome valid 1929 * EX: Exclusive access 1930 * IFSC: Instruction Fault Status Code 1931 */ 1932 1933 #define ISS_SSDE_ISV_SHIFT 24 1934 #define ISS_SSDE_ISV (0x1 << ISS_SSDE_ISV_SHIFT) 1935 1936 #define ISS_SSDE_EX_SHIFT 6 1937 #define ISS_SSDE_EX (0x1 << ISS_SSDE_EX_SHIFT) 1938 1939 #define ISS_SSDE_FSC_MASK 0x3F 1940 #define ISS_SSDE_FSC(x) (x & ISS_SSDE_FSC_MASK) 1941 1942 /* 1943 * Instruction Abort ISS (EL1) 1944 * 24 10 9 5 0 1945 * +--------------+---+--+---+------+ 1946 * |00000000000000|FnV|EA|000| IFSC | 1947 * +--------------+---+--+---+------+ 1948 * 1949 * where: 1950 * FnV: FAR not Valid 1951 * EA: External Abort type 1952 * IFSC: Instruction Fault Status Code 1953 */ 1954 1955 #define ISS_IA_FNV_SHIFT 10 1956 #define ISS_IA_FNV (0x1 << ISS_IA_FNV_SHIFT) 1957 1958 #define ISS_IA_EA_SHIFT 9 1959 #define ISS_IA_EA (0x1 << ISS_IA_EA_SHIFT) 1960 1961 #define ISS_IA_FSC_MASK 0x3F 1962 #define ISS_IA_FSC(x) (x & ISS_IA_FSC_MASK) 1963 1964 1965 /* 1966 * Data Abort ISS (EL1) 1967 * 1968 * 24 10 9 8 7 6 5 0 1969 * +--------------+---+--+--+-----+---+----+ 1970 * |00000000000000|FnV|EA|CM|S1PTW|WnR|DFSC| 1971 * +--------------+---+--+--+-----+---+----+ 1972 * 1973 * where: 1974 * FnV: FAR not Valid 1975 * EA: External Abort type 1976 * CM: Cache Maintenance operation 1977 * WnR: Write not Read 1978 * S1PTW: Stage 2 exception on Stage 1 page table walk 1979 * DFSC: Data Fault Status Code 1980 */ 1981 #define ISS_DA_FNV_SHIFT 10 1982 #define ISS_DA_FNV (0x1 << ISS_DA_FNV_SHIFT) 1983 1984 #define ISS_DA_EA_SHIFT 9 1985 #define ISS_DA_EA (0x1 << ISS_DA_EA_SHIFT) 1986 1987 #define ISS_DA_CM_SHIFT 8 1988 #define ISS_DA_CM (0x1 << ISS_DA_CM_SHIFT) 1989 1990 #define ISS_DA_WNR_SHIFT 6 1991 #define ISS_DA_WNR (0x1 << ISS_DA_WNR_SHIFT) 1992 1993 #define ISS_DA_S1PTW_SHIFT 7 1994 #define ISS_DA_S1PTW (0x1 << ISS_DA_S1PTW_SHIFT) 1995 1996 #define ISS_DA_FSC_MASK 0x3F 1997 #define ISS_DA_FSC(x) (x & ISS_DA_FSC_MASK) 1998 1999 /* 2000 * Floating Point Exception ISS (EL1) 2001 * 2002 * 24 23 22 8 7 4 3 2 1 0 2003 * +-+---+---------------+---+--+---+---+---+---+---+ 2004 * |0|TFV|000000000000000|IDF|00|IXF|UFF|OFF|DZF|IOF| 2005 * +-+---+---------------+---+--+---+---+---+---+---+ 2006 * 2007 * where: 2008 * TFV: Trapped Fault Valid 2009 * IDF: Input Denormal Exception 2010 * IXF: Input Inexact Exception 2011 * UFF: Underflow Exception 2012 * OFF: Overflow Exception 2013 * DZF: Divide by Zero Exception 2014 * IOF: Invalid Operation Exception 2015 */ 2016 #define ISS_FP_TFV_SHIFT 23 2017 #define ISS_FP_TFV (0x1 << ISS_FP_TFV_SHIFT) 2018 2019 #define ISS_FP_IDF_SHIFT 7 2020 #define ISS_FP_IDF (0x1 << ISS_FP_IDF_SHIFT) 2021 2022 #define ISS_FP_IXF_SHIFT 4 2023 #define ISS_FP_IXF (0x1 << ISS_FP_IXF_SHIFT) 2024 2025 #define ISS_FP_UFF_SHIFT 3 2026 #define ISS_FP_UFF (0x1 << ISS_FP_UFF_SHIFT) 2027 2028 #define ISS_FP_OFF_SHIFT 2 2029 #define ISS_FP_OFF (0x1 << ISS_FP_OFF_SHIFT) 2030 2031 #define ISS_FP_DZF_SHIFT 1 2032 #define ISS_FP_DZF (0x1 << ISS_FP_DZF_SHIFT) 2033 2034 #define ISS_FP_IOF_SHIFT 0 2035 #define ISS_FP_IOF (0x1 << ISS_FP_IOF_SHIFT) 2036 2037 /* 2038 * Breakpoint Exception ISS (EL1) 2039 * 24 16 0 2040 * +---------+---------+ 2041 * |000000000| Comment | 2042 * +---------+---------+ 2043 * 2044 * where: 2045 * Comment: Instruction Comment Field Value 2046 */ 2047 #define ISS_BRK_COMMENT_MASK 0xFFFF 2048 #define ISS_BRK_COMMENT(x) (x & ISS_BRK_COMMENT_MASK) 2049 2050 2051 2052 /* 2053 * SError Interrupt, IDS=1 2054 * 24 23 0 2055 * +---+------------------------+ 2056 * |IDS| IMPLEMENTATION DEFINED | 2057 * +---+------------------------+ 2058 * 2059 * where: 2060 * IDS: Implementation-defined syndrome (1) 2061 */ 2062 2063 #define ISS_SEI_IDS_SHIFT 24 2064 #define ISS_SEI_IDS (0x1 << ISS_SEI_IDS_SHIFT) 2065 2066 2067 #if HAS_UCNORMAL_MEM 2068 #define ISS_UC 0x11 2069 #endif /* HAS_UCNORMAL_MEM */ 2070 2071 2072 2073 #if HAS_ARM_FEAT_SME 2074 2075 /* 2076 * SME ISS (EL1) 2077 * 2078 * 24 3 2 0 2079 * +----------------------+----+ 2080 * |0000000000000000000000|SMTC| 2081 * +----------------------+----+ 2082 * 2083 * where: 2084 * SMTC: SME Trap Code 2085 */ 2086 #define ISS_SME_SMTC_CAPCR 0x0 2087 #define ISS_SME_SMTC_MASK 0x7 2088 #define ISS_SME_SMTC(x) ((x) & ISS_SME_SMTC_MASK) 2089 2090 2091 /* 2092 * SME Control Register (EL1) 2093 * 31 30 29 4 3 0 2094 * +----+----+--------------------------+---+ 2095 * |FA64|EZT0|00000000000000000000000000|LEN| 2096 * +----+----+--------------------------+---+ 2097 * 2098 * where: 2099 * FA64: Enable FEAT_SME_FA64 2100 * EZT0: Enable ZT0 2101 * LEN: Effective SVL = (LEN + 1) * 128 2102 */ 2103 2104 #define SMCR_EL1_LEN_MASK 0xf 2105 #if HAS_ARM_FEAT_SME2 2106 #define SMCR_EL1_EZT0 (1ULL << 30) 2107 #endif 2108 #define SMCR_EL1_LEN(x) ((x) & SMCR_EL1_LEN_MASK) 2109 2110 #define SMPRI_EL1_PRIORITY_MASK 0xf 2111 #define SMPRI_EL1_PRIORITY(x) ((x) & SMPRI_EL1_PRIORITY_MASK) 2112 2113 /* 2114 * Streaming Vector Control Register (SVCR) 2115 */ 2116 #define SVCR_ZA_SHIFT (1) 2117 #define SVCR_ZA (1ULL << SVCR_ZA_SHIFT) 2118 #define SVCR_SM_SHIFT (0) 2119 #define SVCR_SM (1ULL << SVCR_SM_SHIFT) 2120 2121 #endif /* HAS_ARM_FEAT_SME */ 2122 2123 /* 2124 * Branch Target Indication Exception ISS 2125 * 24 3 2 0 2126 * +----+-----+ 2127 * |res0|BTYPE| 2128 * +----+-----+ 2129 */ 2130 #define ISS_BTI_BTYPE_SHIFT (0) 2131 #define ISS_BTI_BTYPE_MASK (0x3 << ISS_BTI_BTYPE_SHIFT) 2132 2133 /* 2134 * Physical Address Register (EL1) 2135 */ 2136 #define PAR_F_SHIFT 0 2137 #define PAR_F (0x1 << PAR_F_SHIFT) 2138 2139 #define PLATFORM_SYSCALL_TRAP_NO 0x80000000 2140 2141 #define ARM64_SYSCALL_CODE_REG_NUM (16) 2142 2143 #define ARM64_CLINE_SHIFT 6 2144 2145 #if defined(APPLE_ARM64_ARCH_FAMILY) 2146 #define L2CERRSTS_DATSBEESV (1ULL << 2) /* L2C data single bit ECC error */ 2147 #define L2CERRSTS_DATDBEESV (1ULL << 4) /* L2C data double bit ECC error */ 2148 #endif 2149 2150 /* 2151 * Timer definitions. 2152 */ 2153 #define CNTKCTL_EL1_PL0PTEN (0x1 << 9) /* 1: EL0 access to physical timer regs permitted */ 2154 #define CNTKCTL_EL1_PL0VTEN (0x1 << 8) /* 1: EL0 access to virtual timer regs permitted */ 2155 #define CNTKCTL_EL1_EVENTI_MASK (0x000000f0) /* Mask for bits describing which bit to use for triggering event stream */ 2156 #define CNTKCTL_EL1_EVENTI_SHIFT (0x4) /* Shift for same */ 2157 #define CNTKCTL_EL1_EVENTDIR (0x1 << 3) /* 1: one-to-zero transition of specified bit causes event */ 2158 #define CNTKCTL_EL1_EVNTEN (0x1 << 2) /* 1: enable event stream */ 2159 #define CNTKCTL_EL1_PL0VCTEN (0x1 << 1) /* 1: EL0 access to virtual timebase + frequency reg enabled */ 2160 #define CNTKCTL_EL1_PL0PCTEN (0x1 << 0) /* 1: EL0 access to physical timebase + frequency reg enabled */ 2161 2162 #define CNTV_CTL_EL0_ISTATUS (0x1 << 2) /* (read only): whether interrupt asserted */ 2163 #define CNTV_CTL_EL0_IMASKED (0x1 << 1) /* 1: interrupt masked */ 2164 #define CNTV_CTL_EL0_ENABLE (0x1 << 0) /* 1: virtual timer enabled */ 2165 2166 #define CNTP_CTL_EL0_ISTATUS CNTV_CTL_EL0_ISTATUS 2167 #define CNTP_CTL_EL0_IMASKED CNTV_CTL_EL0_IMASKED 2168 #define CNTP_CTL_EL0_ENABLE CNTV_CTL_EL0_ENABLE 2169 2170 #define MIDR_EL1_REV_SHIFT 0 2171 #define MIDR_EL1_REV_MASK (0xf << MIDR_EL1_REV_SHIFT) 2172 #define MIDR_EL1_PNUM_SHIFT 4 2173 #define MIDR_EL1_PNUM_MASK (0xfff << MIDR_EL1_PNUM_SHIFT) 2174 #define MIDR_EL1_ARCH_SHIFT 16 2175 #define MIDR_EL1_ARCH_MASK (0xf << MIDR_EL1_ARCH_SHIFT) 2176 #define MIDR_EL1_VAR_SHIFT 20 2177 #define MIDR_EL1_VAR_MASK (0xf << MIDR_EL1_VAR_SHIFT) 2178 #define MIDR_EL1_IMP_SHIFT 24 2179 #define MIDR_EL1_IMP_MASK (0xff << MIDR_EL1_IMP_SHIFT) 2180 2181 #define MIDR_FIJI (0x002 << MIDR_EL1_PNUM_SHIFT) 2182 #define MIDR_CAPRI (0x003 << MIDR_EL1_PNUM_SHIFT) 2183 #define MIDR_MAUI (0x004 << MIDR_EL1_PNUM_SHIFT) 2184 #define MIDR_ELBA (0x005 << MIDR_EL1_PNUM_SHIFT) 2185 #define MIDR_CAYMAN (0x006 << MIDR_EL1_PNUM_SHIFT) 2186 #define MIDR_MYST (0x007 << MIDR_EL1_PNUM_SHIFT) 2187 #define MIDR_SKYE_MONSOON (0x008 << MIDR_EL1_PNUM_SHIFT) 2188 #define MIDR_SKYE_MISTRAL (0x009 << MIDR_EL1_PNUM_SHIFT) 2189 #define MIDR_CYPRUS_VORTEX (0x00B << MIDR_EL1_PNUM_SHIFT) 2190 #define MIDR_CYPRUS_TEMPEST (0x00C << MIDR_EL1_PNUM_SHIFT) 2191 #define MIDR_M9 (0x00F << MIDR_EL1_PNUM_SHIFT) 2192 #define MIDR_ARUBA_VORTEX (0x010 << MIDR_EL1_PNUM_SHIFT) 2193 #define MIDR_ARUBA_TEMPEST (0x011 << MIDR_EL1_PNUM_SHIFT) 2194 2195 #ifdef APPLELIGHTNING 2196 #define MIDR_CEBU_LIGHTNING (0x012 << MIDR_EL1_PNUM_SHIFT) 2197 #define MIDR_CEBU_THUNDER (0x013 << MIDR_EL1_PNUM_SHIFT) 2198 #define MIDR_TURKS (0x026 << MIDR_EL1_PNUM_SHIFT) 2199 #endif 2200 2201 #ifdef APPLEFIRESTORM 2202 #define MIDR_SICILY_ICESTORM (0x020 << MIDR_EL1_PNUM_SHIFT) 2203 #define MIDR_SICILY_FIRESTORM (0x021 << MIDR_EL1_PNUM_SHIFT) 2204 #define MIDR_TONGA_ICESTORM (0x022 << MIDR_EL1_PNUM_SHIFT) 2205 #define MIDR_TONGA_FIRESTORM (0x023 << MIDR_EL1_PNUM_SHIFT) 2206 #define MIDR_JADE_CHOP_ICESTORM (0x024 << MIDR_EL1_PNUM_SHIFT) 2207 #define MIDR_JADE_CHOP_FIRESTORM (0x025 << MIDR_EL1_PNUM_SHIFT) 2208 #define MIDR_JADE_DIE_ICESTORM (0x028 << MIDR_EL1_PNUM_SHIFT) 2209 #define MIDR_JADE_DIE_FIRESTORM (0x029 << MIDR_EL1_PNUM_SHIFT) 2210 #endif 2211 2212 #ifdef APPLEAVALANCHE 2213 #define MIDR_ELLIS_BLIZZARD (0x030 << MIDR_EL1_PNUM_SHIFT) 2214 #define MIDR_ELLIS_AVALANCHE (0x031 << MIDR_EL1_PNUM_SHIFT) 2215 #endif 2216 #define MIDR_STATEN_BLIZZARD (0x032 << MIDR_EL1_PNUM_SHIFT) 2217 #define MIDR_STATEN_AVALANCHE (0x033 << MIDR_EL1_PNUM_SHIFT) 2218 #define MIDR_RHODES_CHOP_BLIZZARD (0x034 << MIDR_EL1_PNUM_SHIFT) 2219 #define MIDR_RHODES_CHOP_AVALANCHE (0x035 << MIDR_EL1_PNUM_SHIFT) 2220 #define MIDR_RHODES_DIE_BLIZZARD (0x038 << MIDR_EL1_PNUM_SHIFT) 2221 #define MIDR_RHODES_DIE_AVALANCHE (0x039 << MIDR_EL1_PNUM_SHIFT) 2222 2223 #if defined(APPLEEVEREST) 2224 #define MIDR_CRETE_SAWTOOTH (0x040 << MIDR_EL1_PNUM_SHIFT) 2225 #define MIDR_CRETE_EVEREST (0x041 << MIDR_EL1_PNUM_SHIFT) 2226 #define MIDR_IBIZA_ACCE (0x042 << MIDR_EL1_PNUM_SHIFT) 2227 #define MIDR_IBIZA_ACCP (0x043 << MIDR_EL1_PNUM_SHIFT) 2228 #define MIDR_LOBOS_ACCE (0x044 << MIDR_EL1_PNUM_SHIFT) 2229 #define MIDR_LOBOS_ACCP (0x045 << MIDR_EL1_PNUM_SHIFT) 2230 #define MIDR_CAICOS_ACCE (0x046 << MIDR_EL1_PNUM_SHIFT) 2231 #define MIDR_PALMA_ACCE (0x048 << MIDR_EL1_PNUM_SHIFT) 2232 #define MIDR_PALMA_ACCP (0x049 << MIDR_EL1_PNUM_SHIFT) 2233 #define MIDR_COLL_ACCE (0x050 << MIDR_EL1_PNUM_SHIFT) 2234 #define MIDR_COLL_ACCP (0x051 << MIDR_EL1_PNUM_SHIFT) 2235 #endif /* defined(APPLEEVEREST) */ 2236 2237 /*Donan*/ 2238 #define MIDR_DONAN_ACCE (0x052 << MIDR_EL1_PNUM_SHIFT) 2239 #define MIDR_DONAN_ACCP (0x053 << MIDR_EL1_PNUM_SHIFT) 2240 2241 2242 /* 2243 * Apple-ISA-Extensions ID Register. 2244 */ 2245 #define AIDR_MUL53 (1ULL << 0) 2246 #define AIDR_WKDM (1ULL << 1) 2247 #define AIDR_ARCHRETENTION (1ULL << 2) 2248 2249 2250 2251 2252 /* 2253 * CoreSight debug registers 2254 */ 2255 #define CORESIGHT_ED 0 2256 #define CORESIGHT_CTI 1 2257 #define CORESIGHT_PMU 2 2258 #define CORESIGHT_UTT 3 /* Not truly a coresight thing, but at a fixed convenient location right after the coresight region */ 2259 2260 #define CORESIGHT_OFFSET(x) ((x) * 0x10000) 2261 #define CORESIGHT_REGIONS 4 2262 #define CORESIGHT_SIZE 0x1000 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 /* 2274 * ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 2275 * 2276 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2277 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2278 * | rndr | tlb | ts | fhm | dp | sm4 | sm3 | sha3 | rdm | res0 | atomic | crc32 | sha2 | sha1 | aes | res0 | 2279 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2280 */ 2281 2282 #define ID_AA64ISAR0_EL1_TS_OFFSET 52 2283 #define ID_AA64ISAR0_EL1_TS_MASK (0xfull << ID_AA64ISAR0_EL1_TS_OFFSET) 2284 #define ID_AA64ISAR0_EL1_TS_FLAGM_EN (1ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2285 #define ID_AA64ISAR0_EL1_TS_FLAGM2_EN (2ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2286 2287 #define ID_AA64ISAR0_EL1_FHM_OFFSET 48 2288 #define ID_AA64ISAR0_EL1_FHM_MASK (0xfull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2289 #define ID_AA64ISAR0_EL1_FHM_8_2 (1ull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2290 2291 #define ID_AA64ISAR0_EL1_DP_OFFSET 44 2292 #define ID_AA64ISAR0_EL1_DP_MASK (0xfull << ID_AA64ISAR0_EL1_DP_OFFSET) 2293 #define ID_AA64ISAR0_EL1_DP_EN (1ull << ID_AA64ISAR0_EL1_DP_OFFSET) 2294 2295 #define ID_AA64ISAR0_EL1_SHA3_OFFSET 32 2296 #define ID_AA64ISAR0_EL1_SHA3_MASK (0xfull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2297 #define ID_AA64ISAR0_EL1_SHA3_EN (1ull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2298 2299 #define ID_AA64ISAR0_EL1_RDM_OFFSET 28 2300 #define ID_AA64ISAR0_EL1_RDM_MASK (0xfull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2301 #define ID_AA64ISAR0_EL1_RDM_EN (1ull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2302 2303 #define ID_AA64ISAR0_EL1_ATOMIC_OFFSET 20 2304 #define ID_AA64ISAR0_EL1_ATOMIC_MASK (0xfull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2305 #define ID_AA64ISAR0_EL1_ATOMIC_8_1 (2ull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2306 2307 #define ID_AA64ISAR0_EL1_CRC32_OFFSET 16 2308 #define ID_AA64ISAR0_EL1_CRC32_MASK (0xfull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2309 #define ID_AA64ISAR0_EL1_CRC32_EN (1ull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2310 2311 #define ID_AA64ISAR0_EL1_SHA2_OFFSET 12 2312 #define ID_AA64ISAR0_EL1_SHA2_MASK (0xfull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2313 #define ID_AA64ISAR0_EL1_SHA2_EN (1ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2314 #define ID_AA64ISAR0_EL1_SHA2_512_EN (2ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2315 2316 #define ID_AA64ISAR0_EL1_SHA1_OFFSET 8 2317 #define ID_AA64ISAR0_EL1_SHA1_MASK (0xfull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2318 #define ID_AA64ISAR0_EL1_SHA1_EN (1ull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2319 2320 #define ID_AA64ISAR0_EL1_AES_OFFSET 4 2321 #define ID_AA64ISAR0_EL1_AES_MASK (0xfull << ID_AA64ISAR0_EL1_AES_OFFSET) 2322 #define ID_AA64ISAR0_EL1_AES_EN (1ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2323 #define ID_AA64ISAR0_EL1_AES_PMULL_EN (2ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2324 2325 /* 2326 * ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 1 2327 * 2328 * 63 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2329 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2330 * | res0 | i8mm | dgh | bf16 | specres | sb | frintts | gpi | gpa | lrcpc | fcma | jscvt | api | apa | dpb | 2331 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2332 */ 2333 2334 #define ID_AA64ISAR1_EL1_I8MM_OFFSET 52 2335 #define ID_AA64ISAR1_EL1_I8MM_MASK (0xfull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2336 #define ID_AA64ISAR1_EL1_I8MM_EN (1ull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2337 2338 #define ID_AA64ISAR1_EL1_DGH_OFFSET 48 2339 #define ID_AA64ISAR1_EL1_DGH_MASK (0xfull << ID_AA64ISAR1_EL1_DGH_OFFSET) 2340 2341 #define ID_AA64ISAR1_EL1_BF16_OFFSET 44 2342 #define ID_AA64ISAR1_EL1_BF16_MASK (0xfull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2343 #define ID_AA64ISAR1_EL1_BF16_EN (1ull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2344 2345 #define ID_AA64ISAR1_EL1_SPECRES_OFFSET 40 2346 #define ID_AA64ISAR1_EL1_SPECRES_MASK (0xfull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2347 #define ID_AA64ISAR1_EL1_SPECRES_EN (1ull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2348 2349 #define ID_AA64ISAR1_EL1_SB_OFFSET 36 2350 #define ID_AA64ISAR1_EL1_SB_MASK (0xfull << ID_AA64ISAR1_EL1_SB_OFFSET) 2351 #define ID_AA64ISAR1_EL1_SB_EN (1ull << ID_AA64ISAR1_EL1_SB_OFFSET) 2352 2353 #define ID_AA64ISAR1_EL1_FRINTTS_OFFSET 32 2354 #define ID_AA64ISAR1_EL1_FRINTTS_MASK (0xfull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 2355 #define ID_AA64ISAR1_EL1_FRINTTS_EN (1ull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 2356 2357 #define ID_AA64ISAR1_EL1_GPI_OFFSET 28 2358 #define ID_AA64ISAR1_EL1_GPI_MASK (0xfull << ID_AA64ISAR1_EL1_GPI_OFFSET) 2359 #define ID_AA64ISAR1_EL1_GPI_EN (1ull << ID_AA64ISAR1_EL1_GPI_OFFSET) 2360 2361 #define ID_AA64ISAR1_EL1_GPA_OFFSET 24 2362 #define ID_AA64ISAR1_EL1_GPA_MASK (0xfull << ID_AA64ISAR1_EL1_GPA_OFFSET) 2363 2364 #define ID_AA64ISAR1_EL1_LRCPC_OFFSET 20 2365 #define ID_AA64ISAR1_EL1_LRCPC_MASK (0xfull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2366 #define ID_AA64ISAR1_EL1_LRCPC_EN (1ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2367 #define ID_AA64ISAR1_EL1_LRCP2C_EN (2ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2368 2369 #define ID_AA64ISAR1_EL1_FCMA_OFFSET 16 2370 #define ID_AA64ISAR1_EL1_FCMA_MASK (0xfull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 2371 #define ID_AA64ISAR1_EL1_FCMA_EN (1ull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 2372 2373 #define ID_AA64ISAR1_EL1_JSCVT_OFFSET 12 2374 #define ID_AA64ISAR1_EL1_JSCVT_MASK (0xfull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 2375 #define ID_AA64ISAR1_EL1_JSCVT_EN (1ull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 2376 2377 #define ID_AA64ISAR1_EL1_API_OFFSET 8 2378 #define ID_AA64ISAR1_EL1_API_MASK (0xfull << ID_AA64ISAR1_EL1_API_OFFSET) 2379 #define ID_AA64ISAR1_EL1_API_PAuth_EN (1ull << ID_AA64ISAR1_EL1_API_OFFSET) 2380 #define ID_AA64ISAR1_EL1_API_PAuth2_EN (3ull << ID_AA64ISAR1_EL1_API_OFFSET) 2381 #define ID_AA64ISAR1_EL1_API_FPAC_EN (4ull << ID_AA64ISAR1_EL1_API_OFFSET) 2382 #define ID_AA64ISAR1_EL1_API_FPACCOMBINE (5ull << ID_AA64ISAR1_EL1_API_OFFSET) 2383 2384 #define ID_AA64ISAR1_EL1_APA_OFFSET 4 2385 #define ID_AA64ISAR1_EL1_APA_MASK (0xfull << ID_AA64ISAR1_EL1_APA_OFFSET) 2386 2387 #define ID_AA64ISAR1_EL1_DPB_OFFSET 0 2388 #define ID_AA64ISAR1_EL1_DPB_MASK (0xfull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2389 #define ID_AA64ISAR1_EL1_DPB_EN (1ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2390 #define ID_AA64ISAR1_EL1_DPB2_EN (2ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2391 2392 /* 2393 * ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 2 2394 * 2395 * 63 8 7 4 3 0 2396 * +------+-------+------+ 2397 * | res0 | RPRES | WFxT | 2398 * +------+-------+------+ 2399 */ 2400 2401 #define ID_AA64ISAR2_EL1_RPRES_OFFSET 4 2402 #define ID_AA64ISAR2_EL1_RPRES_MASK (0xfull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 2403 #define ID_AA64ISAR2_EL1_RPRES_EN (1ull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 2404 2405 #define ID_AA64ISAR2_EL1_WFxT_OFFSET 0 2406 #define ID_AA64ISAR2_EL1_WFxT_MASK (0xfull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 2407 #define ID_AA64ISAR2_EL1_WFxT_EN (1ull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 2408 2409 /* 2410 * ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0 2411 * 63 60 59 56 55 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2412 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 2413 * | ECV | FGT | RES0 | ExS | TGran4_2 | TGran64_2 | TGran16_2 | TGran4 | TGran64 | TGran16 | BigEndEL0 | SNSMem | BigEnd | ASIDBits | PARange | 2414 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 2415 */ 2416 2417 #define ID_AA64MMFR0_EL1_ECV_OFFSET 60 2418 #define ID_AA64MMFR0_EL1_ECV_MASK (0xfull << ID_AA64MMFR0_EL1_ECV_OFFSET) 2419 #define ID_AA64MMFR0_EL1_ECV_EN (1ull << ID_AA64MMFR0_EL1_ECV_OFFSET) 2420 2421 /* 2422 * ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2 2423 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 14 8 7 4 3 0 2424 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 2425 * | E0PD | EVT | BBM | TTL | RES0 | FWB | IDS | AT | ST | NV | CCIDX | VARANGE | IESB | LSM | UAO | CnP | 2426 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 2427 */ 2428 2429 #define ID_AA64MMFR2_EL1_AT_OFFSET 32 2430 #define ID_AA64MMFR2_EL1_AT_MASK (0xfull << ID_AA64MMFR2_EL1_AT_OFFSET) 2431 #define ID_AA64MMFR2_EL1_AT_LSE2_EN (1ull << ID_AA64MMFR2_EL1_AT_OFFSET) 2432 2433 /* 2434 * ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 2435 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2436 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 2437 * | CSV3 | CSV2 | RES0 | DIT | AMU | MPAM | SEL2 | SVE | RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | 2438 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 2439 */ 2440 2441 #define ID_AA64PFR0_EL1_CSV3_OFFSET 60 2442 #define ID_AA64PFR0_EL1_CSV3_MASK (0xfull << ID_AA64PFR0_EL1_CSV3_OFFSET) 2443 #define ID_AA64PFR0_EL1_CSV3_EN (1ull << ID_AA64PFR0_EL1_CSV3_OFFSET) 2444 2445 #define ID_AA64PFR0_EL1_CSV2_OFFSET 56 2446 #define ID_AA64PFR0_EL1_CSV2_MASK (0xfull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2447 #define ID_AA64PFR0_EL1_CSV2_EN (1ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2448 #define ID_AA64PFR0_EL1_CSV2_2 (2ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2449 2450 #define ID_AA64PFR0_EL1_DIT_OFFSET 48 2451 #define ID_AA64PFR0_EL1_DIT_MASK (0xfull << ID_AA64PFR0_EL1_DIT_OFFSET) 2452 #define ID_AA64PFR0_EL1_DIT_EN (1ull << ID_AA64PFR0_EL1_DIT_OFFSET) 2453 2454 #define ID_AA64PFR0_EL1_AdvSIMD_OFFSET 20 2455 #define ID_AA64PFR0_EL1_AdvSIMD_MASK (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2456 #define ID_AA64PFR0_EL1_AdvSIMD_HPFPCVT (0x0ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2457 #define ID_AA64PFR0_EL1_AdvSIMD_FP16 (0x1ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2458 #define ID_AA64PFR0_EL1_AdvSIMD_DIS (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2459 2460 /* 2461 * ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 2462 * 63 20 19 16 15 12 11 8 7 4 3 0 2463 * +----------------------------------+-----------+----------+-------+------+------+ 2464 * | RES0 | MPAM_frac | RAS_frac | MTE | SSBS | BT | 2465 * +----------------------------------+-----------+----------+-------+------+------+ 2466 */ 2467 2468 2469 #define ID_AA64PFR1_EL1_SME_OFFSET 24 2470 #define ID_AA64PFR1_EL1_SME_MASK (0xfull << ID_AA64PFR1_EL1_SME_OFFSET) 2471 #define ID_AA64PFR1_EL1_CSV2_frac_OFFSET 32 2472 #define ID_AA64PFR1_EL1_CSV2_frac_MASK (0xfull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 2473 #define ID_AA64PFR1_EL1_CSV2_frac_1p1 (1ull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 2474 #define ID_AA64PFR1_EL1_CSV2_frac_1p2 (2ull << ID_AA64PFR1_EL1_CSV2_frac_OFFSET) 2475 2476 2477 #define ID_AA64PFR1_EL1_SSBS_OFFSET 4 2478 #define ID_AA64PFR1_EL1_SSBS_MASK (0xfull << ID_AA64PFR1_EL1_SSBS_OFFSET) 2479 #define ID_AA64PFR1_EL1_SSBS_EN (1ull << ID_AA64PFR1_EL1_SSBS_OFFSET) 2480 2481 #define ID_AA64PFR1_EL1_BT_OFFSET 0 2482 #define ID_AA64PFR1_EL1_BT_MASK (0xfull << ID_AA64PFR1_EL1_BT_OFFSET) 2483 #define ID_AA64PFR1_EL1_BT_EN (1ull << ID_AA64PFR1_EL1_BT_OFFSET) 2484 2485 /* 2486 * ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 2487 * 2488 * 63 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2489 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 2490 * | res0 | nTLBPA | AFP | HCX | ETS | TWED | XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS | 2491 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 2492 */ 2493 2494 #define ID_AA64MMFR1_EL1_AFP_OFFSET 44 2495 #define ID_AA64MMFR1_EL1_AFP_MASK (0xfull << ID_AA64MMFR1_EL1_AFP_OFFSET) 2496 #define ID_AA64MMFR1_EL1_AFP_EN (1ull << ID_AA64MMFR1_EL1_AFP_OFFSET) 2497 2498 #define ID_AA64MMFR1_EL1_HCX_OFFSET 40 2499 #define ID_AA64MMFR1_EL1_HCX_MASK (0xfull << ID_AA64MMFR1_EL1_HCX_OFFSET) 2500 #define ID_AA64MMFR1_EL1_HCX_EN (1ull << ID_AA64MMFR1_EL1_HCX_OFFSET) 2501 2502 /* 2503 * ID_AA64SMFR0_EL1 - SME Feature ID Register 0 2504 * 2505 * 63 62 60 59 56 55 52 51 49 48 47 44 43 40 39 36 35 34 33 32 31 0 2506 * +------+------+--------+--------+------+--------+--------+------+-------+--------+--------+---------+--------+------+ 2507 * | FA64 | res0 | SMEver | I16I64 | res0 | F64F64 | I16I32 | res0 | I8I32 | F16F32 | B16F32 | BI32I32 | F32F32 | res0 | 2508 * +------+------+--------+--------+------+--------+--------+------+-------+--------+--------+---------+--------+------+ 2509 */ 2510 2511 #define ID_AA64SMFR0_EL1_I16I64_OFFSET 52 2512 #define ID_AA64SMFR0_EL1_I16I64_MASK (0xfull << ID_AA64SMFR0_EL1_I16I64_OFFSET) 2513 #define ID_AA64SMFR0_EL1_I16I64_EN (0xfull << ID_AA64SMFR0_EL1_I16I64_OFFSET) 2514 2515 #define ID_AA64SMFR0_EL1_F64F64_OFFSET 48 2516 #define ID_AA64SMFR0_EL1_F64F64_MASK (1ull << ID_AA64SMFR0_EL1_F64F64_OFFSET) 2517 #define ID_AA64SMFR0_EL1_F64F64_EN (1ull << ID_AA64SMFR0_EL1_F64F64_OFFSET) 2518 2519 #define ID_AA64SMFR0_EL1_I16I32_OFFSET 44 2520 #define ID_AA64SMFR0_EL1_I16I32_MASK (0xfull << ID_AA64SMFR0_EL1_I16I32_OFFSET) 2521 #define ID_AA64SMFR0_EL1_I16I32_EN (0x5ull << ID_AA64SMFR0_EL1_I16I32_OFFSET) 2522 2523 #define ID_AA64SMFR0_EL1_I8I32_OFFSET 36 2524 #define ID_AA64SMFR0_EL1_I8I32_MASK (0xfull << ID_AA64SMFR0_EL1_I8I32_OFFSET) 2525 #define ID_AA64SMFR0_EL1_I8I32_EN (0xfull << ID_AA64SMFR0_EL1_I8I32_OFFSET) 2526 2527 #define ID_AA64SMFR0_EL1_F16F32_OFFSET 35 2528 #define ID_AA64SMFR0_EL1_F16F32_MASK (1ull << ID_AA64SMFR0_EL1_F16F32_OFFSET) 2529 #define ID_AA64SMFR0_EL1_F16F32_EN (1ull << ID_AA64SMFR0_EL1_F16F32_OFFSET) 2530 2531 #define ID_AA64SMFR0_EL1_B16F32_OFFSET 34 2532 #define ID_AA64SMFR0_EL1_B16F32_MASK (1ull << ID_AA64SMFR0_EL1_B16F32_OFFSET) 2533 #define ID_AA64SMFR0_EL1_B16F32_EN (1ull << ID_AA64SMFR0_EL1_B16F32_OFFSET) 2534 2535 #define ID_AA64SMFR0_EL1_BI32I32_OFFSET 33 2536 #define ID_AA64SMFR0_EL1_BI32I32_MASK (1ull << ID_AA64SMFR0_EL1_BI32I32_OFFSET) 2537 #define ID_AA64SMFR0_EL1_BI32I32_EN (1ull << ID_AA64SMFR0_EL1_BI32I32_OFFSET) 2538 2539 #define ID_AA64SMFR0_EL1_F32F32_OFFSET 32 2540 #define ID_AA64SMFR0_EL1_F32F32_MASK (1ull << ID_AA64SMFR0_EL1_F32F32_OFFSET) 2541 #define ID_AA64SMFR0_EL1_F32F32_EN (1ull << ID_AA64SMFR0_EL1_F32F32_OFFSET) 2542 2543 2544 2545 2546 #define APSTATE_G_SHIFT (0) 2547 #define APSTATE_P_SHIFT (1) 2548 #define APSTATE_A_SHIFT (2) 2549 #define APSTATE_AP_MASK ((1ULL << APSTATE_A_SHIFT) | (1ULL << APSTATE_P_SHIFT)) 2550 2551 2552 #define ACTLR_EL1_EnTSO (1ULL << 1) 2553 #define ACTLR_EL1_EnAPFLG (1ULL << 4) 2554 #define ACTLR_EL1_EnAFP (1ULL << 5) 2555 #define ACTLR_EL1_EnPRSV (1ULL << 6) 2556 2557 2558 #if HAS_USAT_BIT 2559 #define ACTLR_EL1_USAT_OFFSET 0 2560 #define ACTLR_EL1_USAT_MASK (1ULL << ACTLR_EL1_USAT_OFFSET) 2561 #define ACTLR_EL1_USAT ACTLR_EL1_USAT_MASK 2562 #endif 2563 2564 2565 2566 2567 2568 2569 #ifdef HAS_DISDDHWP0 2570 #define ACTLR_EL1_DisDDHWP0_OFFSET 17 2571 #define ACTLR_EL1_DisDDHWP0_MASK (1ULL << ACTLR_EL1_DisDDHWP0_OFFSET) 2572 #define ACTLR_EL1_DisDDHWP0 ACTLR_EL1_DisDDHWP0_MASK 2573 #endif /* HAS_DISDDDHWP0 */ 2574 2575 2576 #if defined(HAS_APPLE_PAC) 2577 // The value of ptrauth_string_discriminator("recover"), hardcoded so it can be used from assembly code 2578 #define PAC_DISCRIMINATOR_RECOVER 0x1e02 2579 #endif 2580 2581 2582 #define CTR_EL0_L1Ip_OFFSET 14 2583 #define CTR_EL0_L1Ip_VIPT (2ULL << CTR_EL0_L1Ip_OFFSET) 2584 #define CTR_EL0_L1Ip_PIPT (3ULL << CTR_EL0_L1Ip_OFFSET) 2585 #define CTR_EL0_L1Ip_MASK (3ULL << CTR_EL0_L1Ip_OFFSET) 2586 2587 2588 #ifdef __ASSEMBLER__ 2589 2590 /* 2591 * Conditionally write to system/special-purpose register. 2592 * The register is written to only when the first two arguments 2593 * do not match. If they do match, the macro jumps to a 2594 * caller-provided label. 2595 * The _ISB variant also conditionally issues an ISB after the MSR. 2596 * 2597 * $0 - System/special-purpose register to modify 2598 * $1 - Register containing current FPCR value 2599 * $2 - Register containing expected value 2600 * $3 - Label to jump to when register is already set to expected value 2601 */ 2602 .macro CMSR 2603 cmp $1, $2 2604 2605 /* Skip expensive MSR if not required */ 2606 b.eq $3f 2607 msr $0, $2 2608 .endmacro 2609 2610 .macro CMSR_ISB 2611 CMSR $0, $1, $2, $3 2612 isb sy 2613 .endmacro 2614 2615 /* 2616 * Modify FPCR only if it does not contain the XNU default value. 2617 * $0 - Register containing current FPCR value 2618 * $1 - Scratch register 2619 * $2 - Label to jump to when FPCR is already set to default value 2620 */ 2621 .macro SANITIZE_FPCR 2622 mov $1, #FPCR_DEFAULT 2623 CMSR FPCR, $0, $1, $2 2624 .endmacro 2625 2626 /* 2627 * Family of macros that can be used to protect code sections such that they 2628 * are only executed on a particular SoC/Revision/CPU, and skipped otherwise. 2629 * All macros will forward-jump to 1f when the condition is not matched. 2630 * This label may be defined manually, or implicitly through the use of 2631 * the EXEC_END macro. 2632 * For cores, XX can be: EQ (equal), ALL (don't care). 2633 * For revisions, XX can be: EQ (equal), LO (lower than), HS (higher or same), ALL (don't care). 2634 */ 2635 2636 /* 2637 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 2638 * $1 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2639 * $2 - GPR containing MIDR_EL1 value 2640 * $3 - Scratch register 2641 */ 2642 .macro EXEC_COREEQ_REVEQ 2643 and $3, $2, #MIDR_EL1_PNUM_MASK 2644 cmp $3, $0 2645 b.ne 1f 2646 2647 mov $3, $2 2648 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2649 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2650 cmp $3, $1 2651 b.ne 1f 2652 .endmacro 2653 2654 .macro EXEC_COREEQ_REVLO 2655 and $3, $2, #MIDR_EL1_PNUM_MASK 2656 cmp $3, $0 2657 b.ne 1f 2658 2659 mov $3, $2 2660 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2661 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2662 cmp $3, $1 2663 b.pl 1f 2664 .endmacro 2665 2666 .macro EXEC_COREEQ_REVHS 2667 and $3, $2, #MIDR_EL1_PNUM_MASK 2668 cmp $3, $0 2669 b.ne 1f 2670 2671 mov $3, $2 2672 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2673 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2674 cmp $3, $1 2675 b.mi 1f 2676 .endmacro 2677 2678 /* 2679 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2680 * $1 - GPR containing MIDR_EL1 value 2681 * $2 - Scratch register 2682 */ 2683 .macro EXEC_COREALL_REVEQ 2684 mov $2, $1 2685 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2686 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2687 cmp $2, $0 2688 b.ne 1f 2689 .endmacro 2690 2691 .macro EXEC_COREALL_REVLO 2692 mov $2, $1 2693 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2694 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2695 cmp $2, $0 2696 b.pl 1f 2697 .endmacro 2698 2699 .macro EXEC_COREALL_REVHS 2700 mov $2, $1 2701 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2702 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2703 cmp $2, $0 2704 b.mi 1f 2705 .endmacro 2706 2707 .macro CMP_FOREACH reg, cc, label, car, cdr:vararg 2708 cmp \reg, \car 2709 b.\cc \label 2710 .ifnb \cdr 2711 CMP_FOREACH \reg, \cc, \label, \cdr 2712 .endif 2713 .endm 2714 2715 .macro EXEC_COREIN_REVALL midr_el1, scratch, midr_list:vararg 2716 and \scratch, \midr_el1, #MIDR_EL1_PNUM_MASK 2717 CMP_FOREACH \scratch, eq, Lmatch\@, \midr_list 2718 b 1f 2719 Lmatch\@: 2720 .endm 2721 2722 /* 2723 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 2724 * $1 - GPR containing MIDR_EL1 value 2725 * $2 - Scratch register 2726 */ 2727 .macro EXEC_COREEQ_REVALL 2728 and $2, $1, #MIDR_EL1_PNUM_MASK 2729 cmp $2, $0 2730 b.ne 1f 2731 .endmacro 2732 2733 /* 2734 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2735 * $1 - GPR containing MIDR_EL1 value 2736 * $2 - Scratch register 2737 */ 2738 .macro EXEC_PCORE_REVEQ 2739 ARM64_IS_PCORE $2 2740 cbz $2, 1f 2741 2742 mov $2, $1 2743 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2744 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2745 cmp $2, $0 2746 b.ne 1f 2747 .endmacro 2748 2749 .macro EXEC_PCORE_REVLO 2750 ARM64_IS_PCORE $2 2751 cbz $2, 1f 2752 2753 mov $2, $1 2754 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2755 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2756 cmp $2, $0 2757 b.pl 1f 2758 .endmacro 2759 2760 .macro EXEC_PCORE_REVHS 2761 ARM64_IS_PCORE $2 2762 cbz $2, 1f 2763 2764 mov $2, $1 2765 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2766 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2767 cmp $2, $0 2768 b.mi 1f 2769 .endmacro 2770 2771 .macro EXEC_ECORE_REVEQ 2772 ARM64_IS_ECORE $2 2773 cbz $2, 1f 2774 2775 mov $2, $1 2776 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2777 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2778 cmp $2, $0 2779 b.ne 1f 2780 .endmacro 2781 2782 .macro EXEC_ECORE_REVLO 2783 ARM64_IS_ECORE $2 2784 cbz $2, 1f 2785 2786 mov $2, $1 2787 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2788 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2789 cmp $2, $0 2790 b.pl 1f 2791 .endmacro 2792 2793 .macro EXEC_ECORE_REVHS 2794 ARM64_IS_ECORE $2 2795 cbz $2, 1f 2796 2797 mov $2, $1 2798 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2799 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2800 cmp $2, $0 2801 b.mi 1f 2802 .endmacro 2803 2804 /* 2805 * $0 - GPR containing MIDR_EL1 value 2806 * $1 - Scratch register 2807 */ 2808 .macro EXEC_PCORE_REVALL 2809 ARM64_IS_PCORE $1 2810 cbz $1, 1f 2811 .endmacro 2812 2813 .macro EXEC_ECORE_REVALL 2814 ARM64_IS_ECORE $1 2815 cbz $1, 1f 2816 .endmacro 2817 2818 /* 2819 * Macro that defines the label that all EXEC_COREXX_REVXX macros jump to. 2820 */ 2821 .macro EXEC_END 2822 1: 2823 .endmacro 2824 2825 /* 2826 * Wedges CPUs with a specified core that are below a specified revision. This 2827 * macro is intended for CPUs that have been deprecated in iBoot and may have 2828 * incorrect behavior if they continue running xnu. 2829 */ 2830 .macro DEPRECATE_COREEQ_REVLO core, rev, midr_el1, scratch 2831 EXEC_COREEQ_REVLO \core, \rev, \midr_el1, \scratch 2832 /* BEGIN IGNORE CODESTYLE */ 2833 b . 2834 /* END IGNORE CODESTYLE */ 2835 EXEC_END 2836 .endmacro 2837 2838 /* 2839 * Sets bits in an SPR register. 2840 * arg0: Name of the register to be accessed. 2841 * arg1: Mask of bits to be set. 2842 * arg2: Scratch register 2843 */ 2844 .macro HID_SET_BITS 2845 mrs $2, $0 2846 orr $2, $2, $1 2847 msr $0, $2 2848 .endmacro 2849 2850 /* 2851 * Clears bits in an SPR register. 2852 * arg0: Name of the register to be accessed. 2853 * arg1: Mask of bits to be cleared. 2854 * arg2: Scratch register 2855 */ 2856 .macro HID_CLEAR_BITS 2857 mrs $2, $0 2858 bic $2, $2, $1 2859 msr $0, $2 2860 .endmacro 2861 2862 /* 2863 * Combines the functionality of HID_CLEAR_BITS followed by HID_SET_BITS into 2864 * a single read-modify-write sequence. 2865 * arg0: Name of the register to be accessed. 2866 * arg1: Mask of bits to be cleared. 2867 * arg2: Value to insert 2868 * arg3: Scratch register 2869 */ 2870 .macro HID_INSERT_BITS 2871 mrs $3, $0 2872 bic $3, $3, $1 2873 orr $3, $3, $2 2874 msr $0, $3 2875 .endmacro 2876 2877 /* 2878 * Replaces the value of a field in an implementation-defined system register. 2879 * sreg: system register name 2880 * field: field name within the sysreg, where the assembler symbols 2881 * ARM64_REG_<field>_{shift,width} specify the bounds of the field 2882 * (note that preprocessor macros will not work here) 2883 * value: the value to insert 2884 * scr{1,2}: scratch regs 2885 */ 2886 .macro HID_WRITE_FIELD sreg, field, val, scr1, scr2 2887 mrs \scr1, \sreg 2888 mov \scr2, \val 2889 bfi \scr1, \scr2, ARM64_REG_\sreg\()_\field\()_shift, ARM64_REG_\sreg\()_\field\()_width 2890 msr \sreg, \scr1 2891 .endmacro 2892 2893 /* 2894 * This macro is a replacement for ERET with better security properties. 2895 * 2896 * It prevents "straight-line speculation" (an Arm term) past the ERET. 2897 */ 2898 .macro ERET_NO_STRAIGHT_LINE_SPECULATION 2899 eret 2900 #if __ARM_SB_AVAILABLE__ 2901 sb // Technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 2902 #else /* __ARM_SB_AVAILABLE__ */ 2903 isb // ISB technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 2904 nop // Sequence of six NOPs to pad out and terminate instruction decode group */ 2905 nop 2906 nop 2907 nop 2908 nop 2909 nop 2910 #endif /* !__ARM_SB_AVAILABLE__ */ 2911 .endmacro 2912 2913 2914 #endif /* __ASSEMBLER__ */ 2915 2916 #define MSR(reg, src) __asm__ volatile ("msr " reg ", %0" :: "r" (src)) 2917 #define MRS(dest, reg) __asm__ volatile ("mrs %0, " reg : "=r" (dest)) 2918 2919 #if XNU_MONITOR 2920 #define __ARM_PTE_PHYSMAP__ 1 2921 #define PPL_STATE_KERNEL 0 2922 #define PPL_STATE_DISPATCH 1 2923 #define PPL_STATE_PANIC 2 2924 #define PPL_STATE_EXCEPTION 3 2925 #endif 2926 2927 2928 #endif /* _ARM64_PROC_REG_H_ */ 2929