1 /* 2 * Copyright (c) 2007-2023 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 /* 29 * @OSF_COPYRIGHT@ 30 */ 31 /* CMU_ENDHIST */ 32 /* 33 * Mach Operating System 34 * Copyright (c) 1991,1990 Carnegie Mellon University 35 * All Rights Reserved. 36 * 37 * Permission to use, copy, modify and distribute this software and its 38 * documentation is hereby granted, provided that both the copyright 39 * notice and this permission notice appear in all copies of the 40 * software, derivative works or modified versions, and any portions 41 * thereof, and that both notices appear in supporting documentation. 42 * 43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * Carnegie Mellon requests users of this software to return to 48 * 49 * Software Distribution Coordinator or [email protected] 50 * School of Computer Science 51 * Carnegie Mellon University 52 * Pittsburgh PA 15213-3890 53 * 54 * any improvements or extensions that they make and grant Carnegie Mellon 55 * the rights to redistribute these changes. 56 */ 57 58 /* 59 * Processor registers for ARM/ARM64 60 */ 61 #ifndef _ARM64_PROC_REG_H_ 62 #define _ARM64_PROC_REG_H_ 63 64 #if defined (__arm64__) 65 #include <pexpert/arm64/board_config.h> 66 #elif defined (__arm__) 67 #include <pexpert/arm/board_config.h> 68 #endif 69 70 /* 71 * Processor registers for ARM 72 */ 73 #if __ARM_42BIT_PA_SPACE__ 74 /* For now, force the issue! */ 75 /* We need more VA space for the identity map to bootstrap the MMU */ 76 #undef __ARM64_PMAP_SUBPAGE_L1__ 77 #endif /* __ARM_42BIT_PA_SPACE__ */ 78 79 /* For arm platforms, create one pset per cluster */ 80 #define MAX_PSETS MAX_CPU_CLUSTERS 81 82 /* 83 * The clutch scheduler is enabled only on non-AMP platforms for now. 84 */ 85 #if CONFIG_CLUTCH 86 87 #if __ARM_AMP__ 88 89 /* Enable the Edge scheduler for all AS Mac platforms */ 90 #if XNU_TARGET_OS_OSX 91 #define CONFIG_SCHED_CLUTCH 1 92 #define CONFIG_SCHED_EDGE 1 93 #endif /* XNU_TARGET_OS_OSX */ 94 95 96 #else /* __ARM_AMP__ */ 97 #define CONFIG_SCHED_CLUTCH 1 98 #endif /* __ARM_AMP__ */ 99 100 #endif /* CONFIG_CLUTCH */ 101 102 /* Thread groups are enabled on all ARM platforms (irrespective of scheduler) */ 103 #define CONFIG_THREAD_GROUPS 1 104 105 #ifdef XNU_KERNEL_PRIVATE 106 107 #if __ARM_VFP__ 108 #define ARM_VFP_DEBUG 0 109 #endif /* __ARM_VFP__ */ 110 111 #endif /* XNU_KERNEL_PRIVATE */ 112 113 /* 114 * FSR registers 115 * 116 * CPSR: Current Program Status Register 117 * SPSR: Saved Program Status Registers 118 * 119 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0 120 * +-----------------------------------------------------------+ 121 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE | 122 * +-----------------------------------------------------------+ 123 */ 124 125 /* 126 * Flags 127 */ 128 #define PSR_NF 0x80000000 /* Negative/Less than */ 129 #define PSR_ZF 0x40000000 /* Zero */ 130 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */ 131 #define PSR_VF 0x10000000 /* Overflow */ 132 133 /* 134 * Modified execution mode flags 135 */ 136 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */ 137 138 /* 139 * CPU mode 140 */ 141 #define PSR_USER_MODE 0x00000010 /* User mode */ 142 143 #define PSR_MODE_MASK 0x0000001F 144 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE) 145 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE) 146 147 #define PSR_USERDFLT PSR_USER_MODE 148 149 /* 150 * Cache configuration 151 */ 152 153 #if defined (APPLETYPHOON) 154 155 /* I-Cache */ 156 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 157 158 /* D-Cache */ 159 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ 160 161 #elif defined (APPLETWISTER) 162 163 /* I-Cache */ 164 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 165 166 /* D-Cache */ 167 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 168 169 #elif defined (APPLEHURRICANE) 170 171 /* I-Cache */ 172 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 173 174 /* D-Cache */ 175 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 176 177 #elif defined (APPLEMONSOON) 178 179 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */ 180 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 181 182 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */ 183 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 184 185 #elif defined (APPLEVORTEX) 186 187 /* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */ 188 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 189 190 /* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */ 191 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 192 193 #elif defined (APPLELIGHTNING) 194 195 /* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */ 196 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 197 198 /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */ 199 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 200 201 #elif defined (APPLEFIRESTORM) 202 203 /* I-Cache, 256KB for Firestorm, 128KB for Icestorm, 6-way. */ 204 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ 205 206 /* D-Cache, 160KB for Firestorm, 8-way. 64KB for Icestorm, 6-way. */ 207 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ 208 209 #elif defined (BCM2837) /* Raspberry Pi 3 */ 210 211 /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */ 212 #define MMU_I_CLINE 6 213 214 /* D-Cache. */ 215 #define MMU_CLINE 6 216 217 #elif defined (VMAPPLE) 218 219 /* I-Cache. */ 220 #define MMU_I_CLINE 6 221 222 /* D-Cache. */ 223 #define MMU_CLINE 6 224 225 #else 226 #error processor not supported 227 #endif 228 229 #define MAX_L2_CLINE_BYTES (1 << MAX_L2_CLINE) 230 231 /* 232 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers 233 */ 234 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */ 235 #define ARM_DBG_VR_ADDRESS_MASK64 0xFFFFFFFFFFFFFFFCull /* BVR & WVR */ 236 237 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */ 238 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */ 239 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */ 240 #define ARM_DBGBCR_TYPE_IVA (0 << 21) 241 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */ 242 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20) 243 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14) 244 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13) 245 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */ 246 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */ 247 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */ 248 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */ 249 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */ 250 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */ 251 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0) 252 253 /* 254 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR) 255 */ 256 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55 257 258 /* ARM Debug registers of interest */ 259 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310) 260 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0) 261 262 /* 263 * Main ID Register (MIDR) 264 * 265 * 31 24 23 20 19 16 15 4 3 0 266 * +-----+-----+------+------+-----+ 267 * | IMP | VAR | ARCH | PNUM | REV | 268 * +-----+-----+------+------+-----+ 269 * 270 * where: 271 * IMP: Implementor code 272 * VAR: Variant number 273 * ARCH: Architecture code 274 * PNUM: Primary part number 275 * REV: Minor revision number 276 */ 277 #define MIDR_REV_SHIFT 0 278 #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT) 279 #define MIDR_VAR_SHIFT 20 280 #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT) 281 282 283 #if __ARM_KERNEL_PROTECT__ 284 /* 285 * __ARM_KERNEL_PROTECT__ is a feature intended to guard against potential 286 * architectural or microarchitectural vulnerabilities that could allow cores to 287 * read/access EL1-only mappings while in EL0 mode. This is achieved by 288 * removing as many mappings as possible when the core transitions to EL0 mode 289 * from EL1 mode, and restoring those mappings when the core transitions to EL1 290 * mode from EL0 mode. 291 * 292 * At the moment, this is achieved through use of ASIDs and TCR_EL1. TCR_EL1 is 293 * used to map and unmap the ordinary kernel mappings, by contracting and 294 * expanding translation zone size for TTBR1 when exiting and entering EL1, 295 * respectively: 296 * 297 * Kernel EL0 Mappings: TTBR1 mappings that must remain mapped while the core is 298 * is in EL0. 299 * Kernel EL1 Mappings: TTBR1 mappings that must be mapped while the core is in 300 * EL1. 301 * 302 * T1SZ_USER: T1SZ_BOOT + 1 303 * TTBR1_EL1_BASE_BOOT: (2^64) - (2^(64 - T1SZ_BOOT) 304 * TTBR1_EL1_BASE_USER: (2^64) - (2^(64 - T1SZ_USER) 305 * TTBR1_EL1_MAX: (2^64) - 1 306 * 307 * When in EL1, we program TCR_EL1 (specifically, TCR_EL1.T1SZ) to give the 308 * the following TTBR1 layout: 309 * 310 * TTBR1_EL1_BASE_BOOT TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 311 * +---------------------------------------------------------+ 312 * | Kernel EL0 Mappings | Kernel EL1 Mappings | 313 * +---------------------------------------------------------+ 314 * 315 * And when in EL0, we program TCR_EL1 to give the following TTBR1 layout: 316 * 317 * TTBR1_EL1_BASE_USER TTBR1_EL1_MAX 318 * +---------------------------------------------------------+ 319 * | Kernel EL0 Mappings | 320 * +---------------------------------------------------------+ 321 * 322 * With the current implementation, both the EL0 and EL1 mappings for the kernel 323 * use otherwise empty translation tables for mapping the exception vectors (so 324 * that we do not need to TLB flush the exception vector address when switching 325 * between EL0 and EL1). The rationale here is that the TLBI would require a 326 * DSB, and DSBs can be extremely expensive. 327 * 328 * Each pmap is given two ASIDs: (n & ~1) as an EL0 ASID, and (n | 1) as an EL1 329 * ASID. The core switches between ASIDs on EL transitions, so that the TLB 330 * does not need to be fully invalidated on an EL transition. 331 * 332 * Most kernel mappings will be marked non-global in this configuration, as 333 * global mappings would be visible to userspace unless we invalidate them on 334 * eret. 335 */ 336 #if XNU_MONITOR 337 /* 338 * Please note that because we indirect through the thread register in order to 339 * locate the kernel, and because we unmap most of the kernel, the security 340 * model of the PPL is undermined by __ARM_KERNEL_PROTECT__, as we rely on 341 * kernel controlled data to direct codeflow in the exception vectors. 342 * 343 * If we want to ship XNU_MONITOR paired with __ARM_KERNEL_PROTECT__, we will 344 * need to find a performant solution to this problem. 345 */ 346 #endif 347 #endif /* __ARM_KERNEL_PROTECT */ 348 349 #if ARM_PARAMETERIZED_PMAP 350 /* 351 * ARM_PARAMETERIZED_PMAP configures the kernel to get the characteristics of 352 * the page tables (number of levels, size of the root allocation) from the 353 * pmap data structure, rather than treating them as compile-time constants. 354 * This allows the pmap code to dynamically adjust how it deals with page 355 * tables. 356 */ 357 #endif /* ARM_PARAMETERIZED_PMAP */ 358 359 #if __ARM_MIXED_PAGE_SIZE__ 360 /* 361 * __ARM_MIXED_PAGE_SIZE__ configures the kernel to support page tables that do 362 * not use the kernel page size. This is primarily meant to support running 363 * 4KB page processes on a 16KB page kernel. 364 * 365 * This only covers support in the pmap/machine dependent layers. Any support 366 * elsewhere in the kernel must be managed separately. 367 */ 368 #if !ARM_PARAMETERIZED_PMAP 369 /* 370 * Page tables that use non-kernel page sizes require us to reprogram TCR based 371 * on the page tables we are switching to. This means that the parameterized 372 * pmap support is required. 373 */ 374 #error __ARM_MIXED_PAGE_SIZE__ requires ARM_PARAMETERIZED_PMAP 375 #endif /* !ARM_PARAMETERIZED_PMAP */ 376 #if __ARM_KERNEL_PROTECT__ 377 /* 378 * Because switching the page size requires updating TCR based on the pmap, and 379 * __ARM_KERNEL_PROTECT__ relies on TCR being programmed with constants, XNU 380 * does not currently support support configurations that use both 381 * __ARM_KERNEL_PROTECT__ and __ARM_MIXED_PAGE_SIZE__. 382 */ 383 #error __ARM_MIXED_PAGE_SIZE__ and __ARM_KERNEL_PROTECT__ are mutually exclusive 384 #endif /* __ARM_KERNEL_PROTECT__ */ 385 #endif /* __ARM_MIXED_PAGE_SIZE__ */ 386 387 /* 388 * 64-bit Program Status Register (PSR64) 389 * 390 * 31 27 23 22 21 20 19 10 9 5 4 0 391 * +-+-+-+-+-----+---+--+--+----------+-+-+-+-+-+-----+ 392 * |N|Z|C|V|00000|PAN|SS|IL|0000000000|D|A|I|F|0| M | 393 * +-+-+-+-+-+---+---+--+--+----------+-+-+-+-+-+-----+ 394 * 395 * where: 396 * NZCV: Comparison flags 397 * PAN: Privileged Access Never 398 * SS: Single step 399 * IL: Illegal state 400 * DAIF: Interrupt masks 401 * M: Mode field 402 */ 403 404 #define PSR64_NZCV_SHIFT 28 405 #define PSR64_NZCV_MASK (0xF << PSR64_NZCV_SHIFT) 406 407 #define PSR64_N_SHIFT 31 408 #define PSR64_N (1 << PSR64_N_SHIFT) 409 410 #define PSR64_Z_SHIFT 30 411 #define PSR64_Z (1 << PSR64_Z_SHIFT) 412 413 #define PSR64_C_SHIFT 29 414 #define PSR64_C (1 << PSR64_C_SHIFT) 415 416 #define PSR64_V_SHIFT 28 417 #define PSR64_V (1 << PSR64_V_SHIFT) 418 419 #define PSR64_TCO_SHIFT 25 420 #define PSR64_TCO (1 << PSR64_TCO_SHIFT) 421 422 #define PSR64_DIT_SHIFT 24 423 #define PSR64_DIT (1 << PSR64_DIT_SHIFT) 424 425 #define PSR64_UAO_SHIFT 23 426 #define PSR64_UAO (1 << PSR64_UAO_SHIFT) 427 428 #define PSR64_PAN_SHIFT 22 429 #define PSR64_PAN (1 << PSR64_PAN_SHIFT) 430 431 #define PSR64_SS_SHIFT 21 432 #define PSR64_SS (1 << PSR64_SS_SHIFT) 433 434 #define PSR64_IL_SHIFT 20 435 #define PSR64_IL (1 << PSR64_IL_SHIFT) 436 437 /* 438 * SSBS is bit 12 for A64 SPSR and bit 23 for A32 SPSR 439 * I do not want to talk about it! 440 */ 441 #define PSR64_SSBS_SHIFT_32 23 442 #define PSR64_SSBS_SHIFT_64 12 443 #define PSR64_SSBS_32 (1 << PSR64_SSBS_SHIFT_32) 444 #define PSR64_SSBS_64 (1 << PSR64_SSBS_SHIFT_64) 445 446 /* 447 * msr DAIF, Xn and mrs Xn, DAIF transfer into 448 * and out of bits 9:6 449 */ 450 #define DAIF_DEBUG_SHIFT 9 451 #define DAIF_DEBUGF (1 << DAIF_DEBUG_SHIFT) 452 453 #define DAIF_ASYNC_SHIFT 8 454 #define DAIF_ASYNCF (1 << DAIF_ASYNC_SHIFT) 455 456 #define DAIF_IRQF_SHIFT 7 457 #define DAIF_IRQF (1 << DAIF_IRQF_SHIFT) 458 459 #define DAIF_FIQF_SHIFT 6 460 #define DAIF_FIQF (1 << DAIF_FIQF_SHIFT) 461 462 #define DAIF_ALL (DAIF_DEBUGF | DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 463 #define DAIF_STANDARD_DISABLE (DAIF_ASYNCF | DAIF_IRQF | DAIF_FIQF) 464 465 #define SPSR_INTERRUPTS_ENABLED(x) (!(x & DAIF_FIQF)) 466 467 #if HAS_ARM_FEAT_SSBS2 468 #define PSR64_SSBS_U32_DEFAULT PSR64_SSBS_32 469 #define PSR64_SSBS_U64_DEFAULT PSR64_SSBS_64 470 #define PSR64_SSBS_KRN_DEFAULT PSR64_SSBS_64 471 #else 472 #define PSR64_SSBS_U32_DEFAULT (0) 473 #define PSR64_SSBS_U64_DEFAULT (0) 474 #define PSR64_SSBS_KRN_DEFAULT (0) 475 #endif 476 477 /* 478 * msr DAIFSet, Xn, and msr DAIFClr, Xn transfer 479 * from bits 3:0. 480 */ 481 #define DAIFSC_DEBUGF (1 << 3) 482 #define DAIFSC_ASYNCF (1 << 2) 483 #define DAIFSC_IRQF (1 << 1) 484 #define DAIFSC_FIQF (1 << 0) 485 #define DAIFSC_ALL (DAIFSC_DEBUGF | DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 486 #define DAIFSC_STANDARD_DISABLE (DAIFSC_ASYNCF | DAIFSC_IRQF | DAIFSC_FIQF) 487 #define DAIFSC_NOASYNC (DAIFSC_DEBUGF | DAIFSC_IRQF | DAIFSC_FIQF) 488 489 /* 490 * ARM64_TODO: unify with ARM? 491 */ 492 #define PSR64_CF 0x20000000 /* Carry/Borrow/Extend */ 493 494 #define PSR64_MODE_MASK 0x1F 495 496 #define PSR64_USER_MASK PSR64_NZCV_MASK 497 498 #define PSR64_MODE_USER32_THUMB 0x20 499 500 #define PSR64_MODE_RW_SHIFT 4 501 #define PSR64_MODE_RW_64 0 502 #define PSR64_MODE_RW_32 (0x1 << PSR64_MODE_RW_SHIFT) 503 504 #define PSR64_MODE_EL_SHIFT 2 505 #define PSR64_MODE_EL_MASK (0x3 << PSR64_MODE_EL_SHIFT) 506 #define PSR64_MODE_EL3 (0x3 << PSR64_MODE_EL_SHIFT) 507 #define PSR64_MODE_EL2 (0x2 << PSR64_MODE_EL_SHIFT) 508 #define PSR64_MODE_EL1 (0x1 << PSR64_MODE_EL_SHIFT) 509 #define PSR64_MODE_EL0 0 510 511 #define PSR64_MODE_SPX 0x1 512 #define PSR64_MODE_SP0 0 513 514 #define PSR64_USER32_DEFAULT (PSR64_MODE_RW_32 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U32_DEFAULT) 515 #define PSR64_USER64_DEFAULT (PSR64_MODE_RW_64 | PSR64_MODE_EL0 | PSR64_MODE_SP0 | PSR64_SSBS_U64_DEFAULT) 516 #define PSR64_KERNEL_STANDARD (DAIF_STANDARD_DISABLE | PSR64_MODE_RW_64 | PSR64_MODE_EL1 | PSR64_MODE_SP0 | PSR64_SSBS_KRN_DEFAULT) 517 #if __ARM_PAN_AVAILABLE__ 518 #define PSR64_KERNEL_DEFAULT (PSR64_KERNEL_STANDARD | PSR64_PAN) 519 #else 520 #define PSR64_KERNEL_DEFAULT PSR64_KERNEL_STANDARD 521 #endif 522 523 #define PSR64_IS_KERNEL(x) ((x & PSR64_MODE_EL_MASK) > PSR64_MODE_EL0) 524 #define PSR64_IS_USER(x) ((x & PSR64_MODE_EL_MASK) == PSR64_MODE_EL0) 525 526 #define PSR64_IS_USER32(x) (PSR64_IS_USER(x) && (x & PSR64_MODE_RW_32)) 527 #define PSR64_IS_USER64(x) (PSR64_IS_USER(x) && !(x & PSR64_MODE_RW_32)) 528 529 530 531 /* 532 * System Control Register (SCTLR) 533 */ 534 535 #define SCTLR_OTHER (0) 536 537 #define SCTLR_DSSBS (1ULL << 44) 538 539 540 #define SCTLR_EXTRA (0) 541 542 543 #define SCTLR_RESERVED ((3ULL << 28) | (1ULL << 20)) 544 #if defined(HAS_APPLE_PAC) 545 546 // 31 PACIA_ENABLED AddPACIA and AuthIA functions enabled 547 #define SCTLR_PACIA_ENABLED_SHIFT 31 548 #define SCTLR_PACIA_ENABLED (1ULL << SCTLR_PACIA_ENABLED_SHIFT) 549 // 30 PACIB_ENABLED AddPACIB and AuthIB functions enabled 550 #define SCTLR_PACIB_ENABLED (1ULL << 30) 551 // 29:28 RES1 11 552 // 27 PACDA_ENABLED AddPACDA and AuthDA functions enabled 553 #define SCTLR_PACDA_ENABLED (1ULL << 27) 554 // 13 PACDB_ENABLED AddPACDB and AuthDB functions enabled 555 #define SCTLR_PACDB_ENABLED (1ULL << 13) 556 557 #define SCTLR_JOP_KEYS_ENABLED (SCTLR_PACIA_ENABLED | SCTLR_PACDA_ENABLED | SCTLR_PACDB_ENABLED) 558 #endif /* defined(HAS_APPLE_PAC) */ 559 560 // 26 UCI User Cache Instructions 561 #define SCTLR_UCI_ENABLED (1ULL << 26) 562 563 // 25 EE Exception Endianness 564 #define SCTLR_EE_BIG_ENDIAN (1ULL << 25) 565 566 // 24 E0E EL0 Endianness 567 #define SCTLR_E0E_BIG_ENDIAN (1ULL << 24) 568 569 // 23 SPAN Set PAN 570 #define SCTLR_PAN_UNCHANGED (1ULL << 23) 571 572 // 22 EIS Taking an exception is a context synchronization event 573 #define SCTLR_EIS (1ULL << 22) 574 575 // 21 RES0 0 576 // 20 RES1 1 577 578 // 19 WXN Writeable implies eXecute Never 579 #define SCTLR_WXN_ENABLED (1ULL << 19) 580 581 // 18 nTWE Not trap WFE from EL0 582 #define SCTLR_nTWE_WFE_ENABLED (1ULL << 18) 583 584 // 17 RES0 0 585 586 // 16 nTWI Not trap WFI from EL0 587 #define SCTRL_nTWI_WFI_ENABLED (1ULL << 16) 588 589 // 15 UCT User Cache Type register (CTR_EL0) 590 #define SCTLR_UCT_ENABLED (1ULL << 15) 591 592 // 14 DZE User Data Cache Zero (DC ZVA) 593 #define SCTLR_DZE_ENABLED (1ULL << 14) 594 595 // 12 I Instruction cache enable 596 #define SCTLR_I_ENABLED (1ULL << 12) 597 598 // 11 EOS Exception return is a context synchronization event 599 #define SCTLR_EOS (1ULL << 11) 600 601 // 10 EnRCTX EL0 Access to FEAT_SPECRES speculation restriction instructions 602 #define SCTLR_EnRCTX (1ULL << 10) 603 604 // 9 UMA User Mask Access 605 #define SCTLR_UMA_ENABLED (1ULL << 9) 606 607 // 8 SED SETEND Disable 608 #define SCTLR_SED_DISABLED (1ULL << 8) 609 610 // 7 ITD IT Disable 611 #define SCTLR_ITD_DISABLED (1ULL << 7) 612 613 // 6 RES0 0 614 615 // 5 CP15BEN CP15 Barrier ENable 616 #define SCTLR_CP15BEN_ENABLED (1ULL << 5) 617 618 // 4 SA0 Stack Alignment check for EL0 619 #define SCTLR_SA0_ENABLED (1ULL << 4) 620 621 // 3 SA Stack Alignment check 622 #define SCTLR_SA_ENABLED (1ULL << 3) 623 624 // 2 C Cache enable 625 #define SCTLR_C_ENABLED (1ULL << 2) 626 627 // 1 A Alignment check 628 #define SCTLR_A_ENABLED (1ULL << 1) 629 630 // 0 M MMU enable 631 #define SCTLR_M_ENABLED (1ULL << 0) 632 633 #if __ARM_ARCH_8_5__ 634 #define SCTLR_CSEH_DEFAULT (0) 635 #define SCTLR_DSSBS_DEFAULT SCTLR_DSSBS 636 #else 637 #define SCTLR_CSEH_DEFAULT (SCTLR_EIS | SCTLR_EOS) 638 #define SCTLR_DSSBS_DEFAULT (0) 639 #endif 640 641 #if HAS_APPLE_PAC 642 #define SCTLR_ROP_KEYS_DEFAULT SCTLR_PACIB_ENABLED /* IB is ROP */ 643 #else /* !HAS_APPLE_PAC */ 644 #define SCTLR_ROP_KEYS_DEFAULT 0 645 #endif /* HAS_APPLE_PAC */ 646 647 #if HAS_APPLE_PAC 648 #define SCTLR_JOP_KEYS_DEFAULT SCTLR_JOP_KEYS_ENABLED 649 #else /* !HAS_APPLE_PAC */ 650 #define SCTLR_JOP_KEYS_DEFAULT 0 651 #endif 652 653 #define SCTLR_EL1_DEFAULT \ 654 (SCTLR_RESERVED | SCTLR_UCI_ENABLED | SCTLR_nTWE_WFE_ENABLED | SCTLR_DZE_ENABLED | \ 655 SCTLR_I_ENABLED | SCTLR_SED_DISABLED | SCTLR_CP15BEN_ENABLED | \ 656 SCTLR_SA0_ENABLED | SCTLR_SA_ENABLED | SCTLR_C_ENABLED | SCTLR_M_ENABLED | \ 657 SCTLR_CSEH_DEFAULT | SCTLR_DSSBS_DEFAULT | SCTLR_ROP_KEYS_DEFAULT | \ 658 SCTLR_JOP_KEYS_DEFAULT | SCTLR_OTHER | SCTLR_EXTRA ) 659 660 /* 661 * Coprocessor Access Control Register (CPACR) 662 * 663 * 31 28 27 22 21 20 19 0 664 * +---+---+------+------+--------------------+ 665 * |000|TTA|000000| FPEN |00000000000000000000| 666 * +---+---+------+------+--------------------+ 667 * 668 * where: 669 * TTA: Trace trap 670 * FPEN: Floating point enable 671 */ 672 #define CPACR_TTA_SHIFT 28 673 #define CPACR_TTA (1 << CPACR_TTA_SHIFT) 674 675 676 #define CPACR_FPEN_SHIFT 20 677 #define CPACR_FPEN_EL0_TRAP (0x1 << CPACR_FPEN_SHIFT) 678 #define CPACR_FPEN_ENABLE (0x3 << CPACR_FPEN_SHIFT) 679 680 681 /* 682 * FPSR: Floating Point Status Register 683 * 684 * 31 30 29 28 27 26 7 6 4 3 2 1 0 685 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 686 * | N| Z| C| V|QC|0000000000000000000|IDC|00|IXC|UFC|OFC|DZC|IOC| 687 * +--+--+--+--+--+-------------------+---+--+---+---+---+---+---+ 688 */ 689 690 #define FPSR_N_SHIFT 31 691 #define FPSR_Z_SHIFT 30 692 #define FPSR_C_SHIFT 29 693 #define FPSR_V_SHIFT 28 694 #define FPSR_QC_SHIFT 27 695 #define FPSR_IDC_SHIFT 7 696 #define FPSR_IXC_SHIFT 4 697 #define FPSR_UFC_SHIFT 3 698 #define FPSR_OFC_SHIFT 2 699 #define FPSR_DZC_SHIFT 1 700 #define FPSR_IOC_SHIFT 0 701 #define FPSR_N (1 << FPSR_N_SHIFT) 702 #define FPSR_Z (1 << FPSR_Z_SHIFT) 703 #define FPSR_C (1 << FPSR_C_SHIFT) 704 #define FPSR_V (1 << FPSR_V_SHIFT) 705 #define FPSR_QC (1 << FPSR_QC_SHIFT) 706 #define FPSR_IDC (1 << FPSR_IDC_SHIFT) 707 #define FPSR_IXC (1 << FPSR_IXC_SHIFT) 708 #define FPSR_UFC (1 << FPSR_UFC_SHIFT) 709 #define FPSR_OFC (1 << FPSR_OFC_SHIFT) 710 #define FPSR_DZC (1 << FPSR_DZC_SHIFT) 711 #define FPSR_IOC (1 << FPSR_IOC_SHIFT) 712 713 /* 714 * A mask for all for all of the bits that are not RAZ for FPSR; this 715 * is primarily for converting between a 32-bit view of NEON state 716 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 717 */ 718 #define FPSR_MASK \ 719 (FPSR_N | FPSR_Z | FPSR_C | FPSR_V | FPSR_QC | FPSR_IDC | FPSR_IXC | \ 720 FPSR_UFC | FPSR_OFC | FPSR_DZC | FPSR_IOC) 721 722 /* 723 * FPCR: Floating Point Control Register 724 * 725 * 31 26 25 24 23 21 19 18 15 14 12 11 10 9 8 7 0 726 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 727 * |00000|AHP|DN|FZ|RMODE|STRIDE| 0|LEN|IDE|00|IXE|UFE|OFE|DZE|IOE|00000000| 728 * +-----+---+--+--+-----+------+--+---+---+--+---+---+---+---+---+--------+ 729 */ 730 731 #define FPCR_AHP_SHIFT 26 732 #define FPCR_DN_SHIFT 25 733 #define FPCR_FZ_SHIFT 24 734 #define FPCR_RMODE_SHIFT 22 735 #define FPCR_STRIDE_SHIFT 20 736 #define FPCR_LEN_SHIFT 16 737 #define FPCR_IDE_SHIFT 15 738 #define FPCR_IXE_SHIFT 12 739 #define FPCR_UFE_SHIFT 11 740 #define FPCR_OFE_SHIFT 10 741 #define FPCR_DZE_SHIFT 9 742 #define FPCR_IOE_SHIFT 8 743 #define FPCR_AHP (1 << FPCR_AHP_SHIFT) 744 #define FPCR_DN (1 << FPCR_DN_SHIFT) 745 #define FPCR_FZ (1 << FPCR_FZ_SHIFT) 746 #define FPCR_RMODE (0x3 << FPCR_RMODE_SHIFT) 747 #define FPCR_STRIDE (0x3 << FPCR_STRIDE_SHIFT) 748 #define FPCR_LEN (0x7 << FPCR_LEN_SHIFT) 749 #define FPCR_IDE (1 << FPCR_IDE_SHIFT) 750 #define FPCR_IXE (1 << FPCR_IXE_SHIFT) 751 #define FPCR_UFE (1 << FPCR_UFE_SHIFT) 752 #define FPCR_OFE (1 << FPCR_OFE_SHIFT) 753 #define FPCR_DZE (1 << FPCR_DZE_SHIFT) 754 #define FPCR_IOE (1 << FPCR_IOE_SHIFT) 755 #define FPCR_DEFAULT (0) 756 #define FPCR_DEFAULT_32 (FPCR_DN|FPCR_FZ) 757 758 /* 759 * A mask for all for all of the bits that are not RAZ for FPCR; this 760 * is primarily for converting between a 32-bit view of NEON state 761 * (FPSCR) and a 64-bit view of NEON state (FPSR, FPCR). 762 */ 763 #define FPCR_MASK \ 764 (FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE | FPCR_STRIDE | FPCR_LEN | \ 765 FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE) 766 767 /* 768 * Translation Control Register (TCR) 769 * 770 * Legacy: 771 * 772 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 773 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 774 * | zero |TBI1|TBI0|AS|z| IPS |z|TG1| SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ |z|TG0| SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 775 * +------+----+----+--+-+-----+-+---+-----+-----+-----+----+--+------+-+---+-----+-----+-----+----+-+----+ 776 * 777 * Current (with 16KB granule support): 778 * 779 * 63 39 38 37 36 34 32 30 29 28 27 26 25 24 23 22 21 16 14 13 12 11 10 9 8 7 5 0 780 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 781 * | zero |TBI1|TBI0|AS|z| IPS | TG1 | SH1 |ORGN1|IRGN1|EPD1|A1| T1SZ | TG0 | SH0 |ORGN0|IRGN0|EPD0|z|T0SZ| 782 * +------+----+----+--+-+-----+-----+-----+-----+-----+----+--+------+-----+-----+-----+-----+----+-+----+ 783 * 784 * TBI1: Top Byte Ignored for TTBR1 region 785 * TBI0: Top Byte Ignored for TTBR0 region 786 * AS: ASID Size 787 * IPS: Physical Address Size limit 788 * TG1: Granule Size for TTBR1 region 789 * SH1: Shareability for TTBR1 region 790 * ORGN1: Outer Cacheability for TTBR1 region 791 * IRGN1: Inner Cacheability for TTBR1 region 792 * EPD1: Translation table walk disable for TTBR1 793 * A1: ASID selection from TTBR1 enable 794 * T1SZ: Virtual address size for TTBR1 795 * TG0: Granule Size for TTBR0 region 796 * SH0: Shareability for TTBR0 region 797 * ORGN0: Outer Cacheability for TTBR0 region 798 * IRGN0: Inner Cacheability for TTBR0 region 799 * T0SZ: Virtual address size for TTBR0 800 */ 801 802 #define TCR_T0SZ_SHIFT 0ULL 803 #define TCR_TSZ_BITS 6ULL 804 #define TCR_TSZ_MASK ((1ULL << TCR_TSZ_BITS) - 1ULL) 805 806 #define TCR_IRGN0_SHIFT 8ULL 807 #define TCR_IRGN0_DISABLED (0ULL << TCR_IRGN0_SHIFT) 808 #define TCR_IRGN0_WRITEBACK (1ULL << TCR_IRGN0_SHIFT) 809 #define TCR_IRGN0_WRITETHRU (2ULL << TCR_IRGN0_SHIFT) 810 #define TCR_IRGN0_WRITEBACKNO (3ULL << TCR_IRGN0_SHIFT) 811 812 #define TCR_ORGN0_SHIFT 10ULL 813 #define TCR_ORGN0_DISABLED (0ULL << TCR_ORGN0_SHIFT) 814 #define TCR_ORGN0_WRITEBACK (1ULL << TCR_ORGN0_SHIFT) 815 #define TCR_ORGN0_WRITETHRU (2ULL << TCR_ORGN0_SHIFT) 816 #define TCR_ORGN0_WRITEBACKNO (3ULL << TCR_ORGN0_SHIFT) 817 818 #define TCR_SH0_SHIFT 12ULL 819 #define TCR_SH0_NONE (0ULL << TCR_SH0_SHIFT) 820 #define TCR_SH0_OUTER (2ULL << TCR_SH0_SHIFT) 821 #define TCR_SH0_INNER (3ULL << TCR_SH0_SHIFT) 822 823 #define TCR_TG0_GRANULE_SHIFT (14ULL) 824 #define TCR_TG0_GRANULE_BITS (2ULL) 825 #define TCR_TG0_GRANULE_MASK ((1ULL << TCR_TG0_GRANULE_BITS) - 1ULL) 826 827 #define TCR_TG0_GRANULE_4KB (0ULL << TCR_TG0_GRANULE_SHIFT) 828 #define TCR_TG0_GRANULE_64KB (1ULL << TCR_TG0_GRANULE_SHIFT) 829 #define TCR_TG0_GRANULE_16KB (2ULL << TCR_TG0_GRANULE_SHIFT) 830 831 #if __ARM_16K_PG__ 832 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_16KB) 833 #else 834 #define TCR_TG0_GRANULE_SIZE (TCR_TG0_GRANULE_4KB) 835 #endif 836 837 #define TCR_T1SZ_SHIFT 16ULL 838 839 #define TCR_A1_ASID1 (1ULL << 22ULL) 840 #define TCR_EPD1_TTBR1_DISABLED (1ULL << 23ULL) 841 842 #define TCR_IRGN1_SHIFT 24ULL 843 #define TCR_IRGN1_DISABLED (0ULL << TCR_IRGN1_SHIFT) 844 #define TCR_IRGN1_WRITEBACK (1ULL << TCR_IRGN1_SHIFT) 845 #define TCR_IRGN1_WRITETHRU (2ULL << TCR_IRGN1_SHIFT) 846 #define TCR_IRGN1_WRITEBACKNO (3ULL << TCR_IRGN1_SHIFT) 847 848 #define TCR_ORGN1_SHIFT 26ULL 849 #define TCR_ORGN1_DISABLED (0ULL << TCR_ORGN1_SHIFT) 850 #define TCR_ORGN1_WRITEBACK (1ULL << TCR_ORGN1_SHIFT) 851 #define TCR_ORGN1_WRITETHRU (2ULL << TCR_ORGN1_SHIFT) 852 #define TCR_ORGN1_WRITEBACKNO (3ULL << TCR_ORGN1_SHIFT) 853 854 #define TCR_SH1_SHIFT 28ULL 855 #define TCR_SH1_NONE (0ULL << TCR_SH1_SHIFT) 856 #define TCR_SH1_OUTER (2ULL << TCR_SH1_SHIFT) 857 #define TCR_SH1_INNER (3ULL << TCR_SH1_SHIFT) 858 859 #define TCR_TG1_GRANULE_SHIFT 30ULL 860 861 #define TCR_TG1_GRANULE_16KB (1ULL << TCR_TG1_GRANULE_SHIFT) 862 #define TCR_TG1_GRANULE_4KB (2ULL << TCR_TG1_GRANULE_SHIFT) 863 #define TCR_TG1_GRANULE_64KB (3ULL << TCR_TG1_GRANULE_SHIFT) 864 865 #if __ARM_16K_PG__ 866 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_16KB) 867 #else 868 #define TCR_TG1_GRANULE_SIZE (TCR_TG1_GRANULE_4KB) 869 #endif 870 871 #define TCR_IPS_SHIFT 32ULL 872 #define TCR_IPS_BITS 3ULL 873 #define TCR_IPS_MASK ((1ULL << TCR_IPS_BITS) - 1ULL) 874 #define TCR_IPS_32BITS (0ULL << TCR_IPS_SHIFT) 875 #define TCR_IPS_36BITS (1ULL << TCR_IPS_SHIFT) 876 #define TCR_IPS_40BITS (2ULL << TCR_IPS_SHIFT) 877 #define TCR_IPS_42BITS (3ULL << TCR_IPS_SHIFT) 878 #define TCR_IPS_44BITS (4ULL << TCR_IPS_SHIFT) 879 #define TCR_IPS_48BITS (5ULL << TCR_IPS_SHIFT) 880 881 #define TCR_AS_16BIT_ASID (1ULL << 36) 882 #define TCR_TBI0_TOPBYTE_IGNORED (1ULL << 37) 883 #define TCR_TBI1_TOPBYTE_IGNORED (1ULL << 38) 884 #define TCR_TBID0_TBI_DATA_ONLY (1ULL << 51) 885 #define TCR_TBID1_TBI_DATA_ONLY (1ULL << 52) 886 887 #if defined(HAS_APPLE_PAC) 888 #define TCR_TBID0_ENABLE TCR_TBID0_TBI_DATA_ONLY 889 #define TCR_TBID1_ENABLE TCR_TBID1_TBI_DATA_ONLY 890 #else 891 #define TCR_TBID0_ENABLE 0 892 #define TCR_TBID1_ENABLE 0 893 #endif 894 895 #define TCR_E0PD0_BIT (1ULL << 55) 896 #define TCR_E0PD1_BIT (1ULL << 56) 897 898 #if defined(HAS_E0PD) 899 #define TCR_E0PD_VALUE (TCR_E0PD1_BIT) 900 #else 901 #define TCR_E0PD_VALUE 0 902 #endif 903 904 905 #define TCR_EL1_EXTRA 0 906 907 908 /* 909 * Multiprocessor Affinity Register (MPIDR_EL1) 910 * 911 * +64-----------------------------31+30+29-25+24+23-16+15-8+7--0+ 912 * |000000000000000000000000000000001| U|00000|MT| Aff2|Aff1|Aff0| 913 * +---------------------------------+--+-----+--+-----+----+----+ 914 * 915 * where 916 * U: Uniprocessor 917 * MT: Multi-threading at lowest affinity level 918 * Aff2: "1" - PCORE, "0" - ECORE 919 * Aff1: Cluster ID 920 * Aff0: CPU ID 921 */ 922 #define MPIDR_AFF0_SHIFT 0 923 #define MPIDR_AFF0_WIDTH 8 924 #define MPIDR_AFF0_MASK (((1 << MPIDR_AFF0_WIDTH) - 1) << MPIDR_AFF0_SHIFT) 925 #define MPIDR_AFF1_SHIFT 8 926 #define MPIDR_AFF1_WIDTH 8 927 #define MPIDR_AFF1_MASK (((1 << MPIDR_AFF1_WIDTH) - 1) << MPIDR_AFF1_SHIFT) 928 #define MPIDR_AFF2_SHIFT 16 929 #define MPIDR_AFF2_WIDTH 8 930 #define MPIDR_AFF2_MASK (((1 << MPIDR_AFF2_WIDTH) - 1) << MPIDR_AFF2_SHIFT) 931 932 /* 933 * TXSZ indicates the size of the range a TTBR covers. Currently, 934 * we support the following: 935 * 936 * 4KB pages, full page L1: 39 bit range. 937 * 4KB pages, sub-page L1: 38 bit range. 938 * 16KB pages, full page L1: 47 bit range. 939 * 16KB pages, sub-page L1: 39 bit range. 940 * 16KB pages, two level page tables: 36 bit range. 941 */ 942 #if __ARM_KERNEL_PROTECT__ 943 /* 944 * If we are configured to use __ARM_KERNEL_PROTECT__, the first half of the 945 * address space is used for the mappings that will remain in place when in EL0. 946 * As a result, 1 bit less of address space is available to the rest of the 947 * the kernel. 948 */ 949 #endif /* __ARM_KERNEL_PROTECT__ */ 950 #ifdef __ARM_16K_PG__ 951 #if __ARM64_PMAP_SUBPAGE_L1__ 952 #define T0SZ_BOOT 25ULL 953 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 954 #define T0SZ_BOOT 17ULL 955 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 956 #else /* __ARM_16K_PG__ */ 957 #if __ARM64_PMAP_SUBPAGE_L1__ 958 #define T0SZ_BOOT 26ULL 959 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 960 #define T0SZ_BOOT 25ULL 961 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 962 #endif /* __ARM_16K_PG__ */ 963 964 #if defined(APPLE_ARM64_ARCH_FAMILY) 965 /* T0SZ must be the same as T1SZ */ 966 #define T1SZ_BOOT T0SZ_BOOT 967 #else /* defined(APPLE_ARM64_ARCH_FAMILY) */ 968 #ifdef __ARM_16K_PG__ 969 #if __ARM64_PMAP_SUBPAGE_L1__ 970 #define T1SZ_BOOT 25ULL 971 #else /* !__ARM64_PMAP_SUBPAGE_L1__ */ 972 #define T1SZ_BOOT 17ULL 973 #endif /* !__ARM64_PMAP_SUBPAGE_L1__ */ 974 #else /* __ARM_16K_PG__ */ 975 #if __ARM64_PMAP_SUBPAGE_L1__ 976 #define T1SZ_BOOT 26ULL 977 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 978 #define T1SZ_BOOT 25ULL 979 #endif /*__ARM64_PMAP_SUBPAGE_L1__*/ 980 #endif /* __ARM_16K_PG__ */ 981 #endif /* defined(APPLE_ARM64_ARCH_FAMILY) */ 982 983 #if __ARM_42BIT_PA_SPACE__ 984 #define TCR_IPS_VALUE TCR_IPS_42BITS 985 #else /* !__ARM_42BIT_PA_SPACE__ */ 986 #define TCR_IPS_VALUE TCR_IPS_40BITS 987 #endif /* !__ARM_42BIT_PA_SPACE__ */ 988 989 #if CONFIG_KERNEL_TBI 990 #define TCR_EL1_DTBI (TCR_TBI1_TOPBYTE_IGNORED | TCR_TBID1_ENABLE) 991 #else /* CONFIG_KERNEL_TBI */ 992 #define TCR_EL1_DTBI 0 993 #endif /* CONFIG_KERNEL_TBI */ 994 995 #if HAS_16BIT_ASID 996 #define TCR_EL1_ASID TCR_AS_16BIT_ASID 997 #else /* HAS_16BIT_ASID */ 998 #define TCR_EL1_ASID 0 999 #endif /* HAS_16BIT_ASID */ 1000 1001 #define TCR_EL1_BASE \ 1002 (TCR_IPS_VALUE | TCR_SH0_OUTER | TCR_ORGN0_WRITEBACK | \ 1003 TCR_IRGN0_WRITEBACK | (T0SZ_BOOT << TCR_T0SZ_SHIFT) | \ 1004 TCR_SH1_OUTER | TCR_ORGN1_WRITEBACK | \ 1005 TCR_IRGN1_WRITEBACK | (TCR_TG1_GRANULE_SIZE) | \ 1006 TCR_TBI0_TOPBYTE_IGNORED | (TCR_TBID0_ENABLE) | TCR_E0PD_VALUE | \ 1007 TCR_EL1_DTBI | TCR_EL1_ASID | TCR_EL1_EXTRA) 1008 1009 #if __ARM_KERNEL_PROTECT__ 1010 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1011 #define T1SZ_USER (T1SZ_BOOT + 1) 1012 #define TCR_EL1_USER (TCR_EL1_BASE | (T1SZ_USER << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1013 #else 1014 #define TCR_EL1_BOOT (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_SIZE)) 1015 #endif /* __ARM_KERNEL_PROTECT__ */ 1016 1017 #define TCR_EL1_4KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_4KB)) 1018 #define TCR_EL1_16KB (TCR_EL1_BASE | (T1SZ_BOOT << TCR_T1SZ_SHIFT) | (TCR_TG0_GRANULE_16KB)) 1019 1020 1021 1022 1023 /* 1024 * Monitor Debug System Control Register (MDSCR) 1025 */ 1026 1027 #define MDSCR_TFO_SHIFT 31 1028 #define MDSCR_TFO (1ULL << MDSCR_TFO_SHIFT) 1029 #define MDSCR_RXFULL_SHIFT 30 1030 #define MDSCR_RXFULL (1ULL << MDSCR_RXFULL_SHIFT) 1031 #define MDSCR_TXFULL_SHIFT 29 1032 #define MDSCR_TXFULL (1ULL << MDSCR_TXFULL_SHIFT) 1033 #define MDSCR_RXO_SHIFT 27 1034 #define MDSCR_RXO (1ULL << MDSCR_RXO_SHIFT) 1035 #define MDSCR_TXU_SHIFT 26 1036 #define MDSCR_TXU (1ULL << MDSCR_TXU_SHIFT) 1037 #define MDSCR_INTDIS_SHIFT 22 1038 #define MDSCR_INTDIS_MASK (0x2U << MDSCR_INTDIS_SHIFT) 1039 #define MDSCR_TDA_SHIFT 21 1040 #define MDSCR_TDA (1ULL << MDSCR_TDA_SHIFT) 1041 #define MDSCR_SC2_SHIFT 19 1042 #define MDSCR_SC2 (1ULL << MDSCR_SC2_SHIFT) 1043 #define MDSCR_MDE_SHIFT 15 1044 #define MDSCR_MDE (1ULL << MDSCR_MDE_SHIFT) 1045 #define MDSCR_HDE_SHIFT 14 1046 #define MDSCR_HDE (1ULL << MDSCR_HDE_SHIFT) 1047 #define MDSCR_KDE_SHIFT 13 1048 #define MDSCR_KDE (1ULL << MDSCR_KDE_SHIFT) 1049 #define MDSCR_TDCC_SHIFT 12 1050 #define MDSCR_TDCC (1ULL << MDSCR_TDCC_SHIFT) 1051 #define MDSCR_ERR_SHIFT 6 1052 #define MDSCR_ERR (1ULL << MDSCR_ERR_SHIFT) 1053 #define MDSCR_SS_SHIFT 0 1054 #define MDSCR_SS (1ULL << MDSCR_SS_SHIFT) 1055 1056 /* 1057 * Translation Table Base Register (TTBR) 1058 * 1059 * 63 48 47 x x-1 0 1060 * +--------+------------------+------+ 1061 * | ASID | Base Address | zero | 1062 * +--------+------------------+------+ 1063 * 1064 */ 1065 #define TTBR_ASID_SHIFT 48 1066 #define TTBR_ASID_MASK 0xffff000000000000 1067 1068 #define TTBR_BADDR_MASK 0x0000ffffffffffff 1069 1070 /* 1071 * Memory Attribute Indirection Register 1072 * 1073 * 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 1074 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1075 * | Attr7 | Attr6 | Attr5 | Attr4 | Attr3 | Attr2 | Attr1 | Attr0 | 1076 * +-------+-------+-------+-------+-------+-------+-------+-------+ 1077 * 1078 */ 1079 1080 #define MAIR_ATTR_SHIFT(x) (8*(x)) 1081 1082 /* Strongly ordered or device memory attributes */ 1083 #define MAIR_OUTER_STRONGLY_ORDERED 0x0 1084 #define MAIR_OUTER_DEVICE 0x0 1085 1086 #define MAIR_INNER_STRONGLY_ORDERED 0x0 1087 #define MAIR_INNER_DEVICE 0x4 1088 1089 /* Normal memory attributes */ 1090 #define MAIR_OUTER_NON_CACHEABLE 0x40 1091 #define MAIR_OUTER_WRITE_THROUGH 0x80 1092 #define MAIR_OUTER_WRITE_BACK 0xc0 1093 1094 #define MAIR_INNER_NON_CACHEABLE 0x4 1095 #define MAIR_INNER_WRITE_THROUGH 0x8 1096 #define MAIR_INNER_WRITE_BACK 0xc 1097 1098 /* Allocate policy for cacheable memory */ 1099 #define MAIR_OUTER_WRITE_ALLOCATE 0x10 1100 #define MAIR_OUTER_READ_ALLOCATE 0x20 1101 1102 #define MAIR_INNER_WRITE_ALLOCATE 0x1 1103 #define MAIR_INNER_READ_ALLOCATE 0x2 1104 1105 /* Memory Atribute Encoding */ 1106 1107 /* 1108 * Device memory types: 1109 * G (gathering): multiple reads/writes can be combined 1110 * R (reordering): reads or writes may reach device out of program order 1111 * E (early-acknowledge): writes may return immediately (e.g. PCIe posted writes) 1112 */ 1113 #if HAS_FEAT_XS 1114 1115 #define MAIR_DISABLE 0x01 /* Device Memory, nGnRnE (strongly ordered), XS=0 */ 1116 #define MAIR_POSTED_XS 0x04 /* Device Memory, nGnRE (strongly ordered, posted writes), XS=1 */ 1117 #define MAIR_POSTED_COMBINED_REORDERED_XS 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=1 */ 1118 #define MAIR_POSTED_COMBINED_REORDERED 0x0D /* Device Memory, GRE (reorderable, gathered writes, posted writes), XS=0 */ 1119 #define MAIR_WRITECOMB 0x40 /* Normal Memory, Non-Cacheable, XS=0 */ 1120 #define MAIR_WRITETHRU 0xA0 /* Normal Memory, Write-through, XS=0 */ 1121 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Write-back, XS=0 */ 1122 1123 /* 1124 * Memory Attribute Index. If these values change, please also update the pmap 1125 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1126 */ 1127 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1128 #define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1129 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1130 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1131 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory) */ 1132 #define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1133 #define CACHE_ATTRINDX_POSTED_XS 0x5 /* no cache, no buffer, posted writes (device memory), XS=1 */ 1134 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_POSTED_XS /* posted mappings use XS by default */ 1135 #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE /* no need for device-nGRE on newer SoCs, fallback to nGnRnE */ 1136 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x6 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=0 */ 1137 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED_XS 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory), XS=1 */ 1138 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1139 #define CACHE_ATTRINDX_N_INDICES (8ULL) 1140 1141 #else 1142 1143 #define MAIR_DISABLE 0x00 /* Device Memory, nGnRnE (strongly ordered) */ 1144 #define MAIR_POSTED 0x04 /* Device Memory, nGnRE (strongly ordered, posted writes) */ 1145 #define MAIR_POSTED_REORDERED 0x08 /* Device Memory, nGRE (reorderable, posted writes) */ 1146 #define MAIR_POSTED_COMBINED_REORDERED 0x0C /* Device Memory, GRE (reorderable, gathered writes, posted writes) */ 1147 #define MAIR_WRITECOMB 0x44 /* Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable */ 1148 #define MAIR_WRITETHRU 0xBB /* Normal Memory, Outer Write-through, Inner Write-through */ 1149 #define MAIR_WRITEBACK 0xFF /* Normal Memory, Outer Write-back, Inner Write-back */ 1150 1151 /* 1152 * Memory Attribute Index. If these values change, please also update the pmap 1153 * LLDB macros that rely on this value (e.g., PmapDecodeTTEARM64). 1154 */ 1155 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled (normal memory) */ 1156 #define CACHE_ATTRINDX_INNERWRITEBACK CACHE_ATTRINDX_WRITEBACK /* legacy compatibility only */ 1157 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes (normal memory) */ 1158 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled (normal memory) */ 1159 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer (device memory) */ 1160 #define CACHE_ATTRINDX_RESERVED 0x4 /* reserved for internal use */ 1161 #define CACHE_ATTRINDX_POSTED 0x5 /* no cache, no buffer, posted writes (device memory) */ 1162 #define CACHE_ATTRINDX_POSTED_REORDERED 0x6 /* no cache, reorderable access, posted writes (device memory) */ 1163 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED 0x7 /* no cache, write gathering, reorderable access, posted writes (device memory) */ 1164 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK 1165 #define CACHE_ATTRINDX_N_INDICES (8ULL) 1166 1167 #endif /* HAS_FEAT_XS */ 1168 1169 #if HAS_UCNORMAL_MEM 1170 #define CACHE_ATTRINDX_RT CACHE_ATTRINDX_WRITECOMB 1171 #else 1172 #define CACHE_ATTRINDX_RT CACHE_ATTRINDX_DISABLE 1173 #endif /* HAS_UCNORMAL_MEM */ 1174 1175 1176 1177 /* 1178 * Access protection bit values (TTEs and PTEs), stage 1 1179 * 1180 * Bit 1 controls access type (1=RO, 0=RW), bit 0 controls user (1=access, 0=no access) 1181 */ 1182 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */ 1183 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */ 1184 #define AP_RONA 0x2 /* priv=read-only, user=no-access */ 1185 #define AP_RORO 0x3 /* priv=read-only, user=read-only */ 1186 #define AP_MASK 0x3 /* mask to find ap bits */ 1187 1188 /* 1189 * Shareability attributes 1190 */ 1191 #define SH_NONE 0x0 /* Non shareable */ 1192 #define SH_NONE 0x0 /* Device shareable */ 1193 #define SH_DEVICE 0x2 /* Normal memory Inner non shareable - Outer non shareable */ 1194 #define SH_OUTER_MEMORY 0x2 /* Normal memory Inner shareable - Outer shareable */ 1195 #define SH_INNER_MEMORY 0x3 /* Normal memory Inner shareable - Outer non shareable */ 1196 1197 1198 /* 1199 * ARM Page Granule 1200 */ 1201 #ifdef __ARM_16K_PG__ 1202 #define ARM_PGSHIFT 14 1203 #else 1204 #define ARM_PGSHIFT 12 1205 #endif 1206 #define ARM_PGBYTES (1 << ARM_PGSHIFT) 1207 #define ARM_PGMASK (ARM_PGBYTES-1) 1208 1209 /* 1210 * L0 Translation table 1211 * 1212 * 4KB granule size: 1213 * Each translation table is 4KB 1214 * 512 64-bit entries of 512GB (2^39) of address space. 1215 * Covers 256TB (2^48) of address space. 1216 * 1217 * 16KB granule size: 1218 * Each translation table is 16KB 1219 * 2 64-bit entries of 128TB (2^47) of address space. 1220 * Covers 256TB (2^48) of address space. 1221 */ 1222 1223 /* 16K L0 */ 1224 #define ARM_16K_TT_L0_SIZE 0x0000800000000000ULL /* size of area covered by a tte */ 1225 #define ARM_16K_TT_L0_OFFMASK 0x00007fffffffffffULL /* offset within an L0 entry */ 1226 #define ARM_16K_TT_L0_SHIFT 47 /* page descriptor shift */ 1227 #define ARM_16K_TT_L0_INDEX_MASK 0x0000800000000000ULL /* mask for getting index in L0 table from virtual address */ 1228 1229 /* 4K L0 */ 1230 #define ARM_4K_TT_L0_SIZE 0x0000008000000000ULL /* size of area covered by a tte */ 1231 #define ARM_4K_TT_L0_OFFMASK 0x0000007fffffffffULL /* offset within an L0 entry */ 1232 #define ARM_4K_TT_L0_SHIFT 39 /* page descriptor shift */ 1233 #define ARM_4K_TT_L0_INDEX_MASK 0x0000ff8000000000ULL /* mask for getting index in L0 table from virtual address */ 1234 1235 /* 1236 * L1 Translation table 1237 * 1238 * 4KB granule size: 1239 * Each translation table is 4KB 1240 * 512 64-bit entries of 1GB (2^30) of address space. 1241 * Covers 512GB (2^39) of address space. 1242 * 1243 * 16KB granule size: 1244 * Each translation table is 16KB 1245 * 2048 64-bit entries of 64GB (2^36) of address space. 1246 * Covers 128TB (2^47) of address space. 1247 */ 1248 1249 /* 16K L1 */ 1250 #define ARM_16K_TT_L1_SIZE 0x0000001000000000ULL /* size of area covered by a tte */ 1251 #define ARM_16K_TT_L1_OFFMASK 0x0000000fffffffffULL /* offset within an L1 entry */ 1252 #define ARM_16K_TT_L1_SHIFT 36 /* page descriptor shift */ 1253 #if __ARM64_PMAP_SUBPAGE_L1__ && __ARM_16K_PG__ 1254 /* This config supports 512GB per TTBR. */ 1255 #define ARM_16K_TT_L1_INDEX_MASK 0x0000007000000000ULL /* mask for getting index into L1 table from virtual address */ 1256 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1257 #define ARM_16K_TT_L1_INDEX_MASK 0x00007ff000000000ULL /* mask for getting index into L1 table from virtual address */ 1258 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1259 1260 /* 4K L1 */ 1261 #define ARM_4K_TT_L1_SIZE 0x0000000040000000ULL /* size of area covered by a tte */ 1262 #define ARM_4K_TT_L1_OFFMASK 0x000000003fffffffULL /* offset within an L1 entry */ 1263 #define ARM_4K_TT_L1_SHIFT 30 /* page descriptor shift */ 1264 #if __ARM64_PMAP_SUBPAGE_L1__ && !__ARM_16K_PG__ 1265 /* This config supports 256GB per TTBR. */ 1266 #define ARM_4K_TT_L1_INDEX_MASK 0x0000003fc0000000ULL /* mask for getting index into L1 table from virtual address */ 1267 #else /* __ARM64_PMAP_SUBPAGE_L1__ */ 1268 #define ARM_4K_TT_L1_INDEX_MASK 0x0000007fc0000000ULL /* mask for getting index into L1 table from virtual address */ 1269 #endif /* __ARM64_PMAP_SUBPAGE_L1__ */ 1270 1271 /* some sugar for getting pointers to page tables and entries */ 1272 1273 #define L1_TABLE_INDEX(va) (((va) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT) 1274 #define L2_TABLE_INDEX(va) (((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT) 1275 #define L3_TABLE_INDEX(va) (((va) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT) 1276 1277 #define L2_TABLE_VA(tte) ((tt_entry_t*) phystokv((*(tte)) & ARM_TTE_TABLE_MASK)) 1278 #define L3_TABLE_VA(tte2) ((pt_entry_t*) phystokv((*(tte2)) & ARM_TTE_TABLE_MASK)) 1279 1280 /* 1281 * L2 Translation table 1282 * 1283 * 4KB granule size: 1284 * Each translation table is 4KB 1285 * 512 64-bit entries of 2MB (2^21) of address space. 1286 * Covers 1GB (2^30) of address space. 1287 * 1288 * 16KB granule size: 1289 * Each translation table is 16KB 1290 * 2048 64-bit entries of 32MB (2^25) of address space. 1291 * Covers 64GB (2^36) of address space. 1292 */ 1293 1294 /* 16K L2 */ 1295 #define ARM_16K_TT_L2_SIZE 0x0000000002000000ULL /* size of area covered by a tte */ 1296 #define ARM_16K_TT_L2_OFFMASK 0x0000000001ffffffULL /* offset within an L2 entry */ 1297 #define ARM_16K_TT_L2_SHIFT 25 /* page descriptor shift */ 1298 #define ARM_16K_TT_L2_INDEX_MASK 0x0000000ffe000000ULL /* mask for getting index in L2 table from virtual address */ 1299 1300 /* 4K L2 */ 1301 #define ARM_4K_TT_L2_SIZE 0x0000000000200000ULL /* size of area covered by a tte */ 1302 #define ARM_4K_TT_L2_OFFMASK 0x00000000001fffffULL /* offset within an L2 entry */ 1303 #define ARM_4K_TT_L2_SHIFT 21 /* page descriptor shift */ 1304 #define ARM_4K_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */ 1305 1306 /* 1307 * L3 Translation table 1308 * 1309 * 4KB granule size: 1310 * Each translation table is 4KB 1311 * 512 64-bit entries of 4KB (2^12) of address space. 1312 * Covers 2MB (2^21) of address space. 1313 * 1314 * 16KB granule size: 1315 * Each translation table is 16KB 1316 * 2048 64-bit entries of 16KB (2^14) of address space. 1317 * Covers 32MB (2^25) of address space. 1318 */ 1319 1320 /* 16K L3 */ 1321 #define ARM_16K_TT_L3_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1322 #define ARM_16K_TT_L3_OFFMASK 0x0000000000003fffULL /* offset within L3 PTE */ 1323 #define ARM_16K_TT_L3_SHIFT 14 /* page descriptor shift */ 1324 #define ARM_16K_TT_L3_INDEX_MASK 0x0000000001ffc000ULL /* mask for page descriptor index */ 1325 1326 /* 4K L3 */ 1327 #define ARM_4K_TT_L3_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1328 #define ARM_4K_TT_L3_OFFMASK 0x0000000000000fffULL /* offset within L3 PTE */ 1329 #define ARM_4K_TT_L3_SHIFT 12 /* page descriptor shift */ 1330 #define ARM_4K_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */ 1331 1332 #ifdef __ARM_16K_PG__ 1333 1334 /* Native L0 defines */ 1335 #define ARM_TT_L0_SIZE ARM_16K_TT_L0_SIZE 1336 #define ARM_TT_L0_OFFMASK ARM_16K_TT_L0_OFFMASK 1337 #define ARM_TT_L0_SHIFT ARM_16K_TT_L0_SHIFT 1338 #define ARM_TT_L0_INDEX_MASK ARM_16K_TT_L0_INDEX_MASK 1339 1340 /* Native L1 defines */ 1341 #define ARM_TT_L1_SIZE ARM_16K_TT_L1_SIZE 1342 #define ARM_TT_L1_OFFMASK ARM_16K_TT_L1_OFFMASK 1343 #define ARM_TT_L1_SHIFT ARM_16K_TT_L1_SHIFT 1344 #define ARM_TT_L1_INDEX_MASK ARM_16K_TT_L1_INDEX_MASK 1345 1346 /* Native L2 defines */ 1347 #define ARM_TT_L2_SIZE ARM_16K_TT_L2_SIZE 1348 #define ARM_TT_L2_OFFMASK ARM_16K_TT_L2_OFFMASK 1349 #define ARM_TT_L2_SHIFT ARM_16K_TT_L2_SHIFT 1350 #define ARM_TT_L2_INDEX_MASK ARM_16K_TT_L2_INDEX_MASK 1351 1352 /* Native L3 defines */ 1353 #define ARM_TT_L3_SIZE ARM_16K_TT_L3_SIZE 1354 #define ARM_TT_L3_OFFMASK ARM_16K_TT_L3_OFFMASK 1355 #define ARM_TT_L3_SHIFT ARM_16K_TT_L3_SHIFT 1356 #define ARM_TT_L3_INDEX_MASK ARM_16K_TT_L3_INDEX_MASK 1357 1358 #else /* !__ARM_16K_PG__ */ 1359 1360 /* Native L0 defines */ 1361 #define ARM_TT_L0_SIZE ARM_4K_TT_L0_SIZE 1362 #define ARM_TT_L0_OFFMASK ARM_4K_TT_L0_OFFMASK 1363 #define ARM_TT_L0_SHIFT ARM_4K_TT_L0_SHIFT 1364 #define ARM_TT_L0_INDEX_MASK ARM_4K_TT_L0_INDEX_MASK 1365 1366 /* Native L1 defines */ 1367 #define ARM_TT_L1_SIZE ARM_4K_TT_L1_SIZE 1368 #define ARM_TT_L1_OFFMASK ARM_4K_TT_L1_OFFMASK 1369 #define ARM_TT_L1_SHIFT ARM_4K_TT_L1_SHIFT 1370 #define ARM_TT_L1_INDEX_MASK ARM_4K_TT_L1_INDEX_MASK 1371 1372 /* Native L2 defines */ 1373 #define ARM_TT_L2_SIZE ARM_4K_TT_L2_SIZE 1374 #define ARM_TT_L2_OFFMASK ARM_4K_TT_L2_OFFMASK 1375 #define ARM_TT_L2_SHIFT ARM_4K_TT_L2_SHIFT 1376 #define ARM_TT_L2_INDEX_MASK ARM_4K_TT_L2_INDEX_MASK 1377 1378 /* Native L3 defines */ 1379 #define ARM_TT_L3_SIZE ARM_4K_TT_L3_SIZE 1380 #define ARM_TT_L3_OFFMASK ARM_4K_TT_L3_OFFMASK 1381 #define ARM_TT_L3_SHIFT ARM_4K_TT_L3_SHIFT 1382 #define ARM_TT_L3_INDEX_MASK ARM_4K_TT_L3_INDEX_MASK 1383 1384 #endif /* !__ARM_16K_PG__ */ 1385 1386 /* 1387 * Convenience definitions for: 1388 * ARM_TT_LEAF: The last level of the configured page table format. 1389 * ARM_TT_TWIG: The second to last level of the configured page table format. 1390 * ARM_TT_ROOT: The first level of the configured page table format. 1391 * 1392 * My apologies to any botanists who may be reading this. 1393 */ 1394 #define ARM_TT_LEAF_SIZE ARM_TT_L3_SIZE 1395 #define ARM_TT_LEAF_OFFMASK ARM_TT_L3_OFFMASK 1396 #define ARM_TT_LEAF_SHIFT ARM_TT_L3_SHIFT 1397 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L3_INDEX_MASK 1398 1399 #define ARM_TT_TWIG_SIZE ARM_TT_L2_SIZE 1400 #define ARM_TT_TWIG_OFFMASK ARM_TT_L2_OFFMASK 1401 #define ARM_TT_TWIG_SHIFT ARM_TT_L2_SHIFT 1402 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L2_INDEX_MASK 1403 1404 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE 1405 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK 1406 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT 1407 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK 1408 1409 /* 1410 * 4KB granule size: 1411 * 1412 * Level 0 Translation Table Entry 1413 * 1414 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1415 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1416 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1417 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1418 * 1419 * Level 1 Translation Table Entry 1420 * 1421 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1422 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1423 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 1424 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1425 * 1426 * Level 1 Translation Block Entry 1427 * 1428 * 63 59 58 55 54 53 52 51 48 47 30 29 12 11 10 9 8 7 6 5 4 2 1 0 1429 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1430 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:30] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1431 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1432 * 1433 * Level 2 Translation Table Entry 1434 * 1435 * 63 62 61 60 59 58 52 51 48 47 12 11 2 1 0 1436 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1437 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 1438 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1439 * 1440 * Level 2 Translation Block Entry 1441 * 1442 * 63 59 58 55 54 53 52 51 48 47 21 20 12 11 10 9 8 7 6 5 4 2 1 0 1443 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1444 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:21] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1445 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1446 * 1447 * 16KB granule size: 1448 * 1449 * Level 0 Translation Table Entry 1450 * 1451 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1452 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1453 * |NS| AP |XN|PXN|ignored| zero | L1TableOutputAddress |ignored|1|V| 1454 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1455 * 1456 * Level 1 Translation Table Entry 1457 * 1458 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1459 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1460 * |NS| AP |XN|PXN|ignored| zero | L2TableOutputAddress |ignored|1|V| 1461 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1462 * 1463 * Level 2 Translation Table Entry 1464 * 1465 * 63 62 61 60 59 58 52 51 48 47 14 13 2 1 0 1466 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1467 * |NS| AP |XN|PXN|ignored| zero | L3TableOutputAddress |ignored|1|V| 1468 * +--+-----+--+---+-------+------+----------------------+-------+-+-+ 1469 * 1470 * Level 2 Translation Block Entry 1471 * 1472 * 63 59 58 55 54 53 52 51 48 47 25 24 12 11 10 9 8 7 6 5 4 2 1 0 1473 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1474 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:25] | zero |nG|AF| SH | AP |NS|AttrIdx|0|V| 1475 * +-----+------+--+---+----+------+----------------------+------+--+--+----+----+--+-------+-+-+ 1476 * 1477 * where: 1478 * nG: notGlobal bit 1479 * SH: Shareability field 1480 * AP: access protection 1481 * XN: eXecute Never bit 1482 * PXN: Privilege eXecute Never bit 1483 * NS: Non-Secure bit 1484 * HINT: 16 entry continuguous output hint 1485 * AttrIdx: Memory Attribute Index 1486 */ 1487 1488 #define TTE_SHIFT 3 /* shift width of a tte (sizeof(tte) == (1 << TTE_SHIFT)) */ 1489 #ifdef __ARM_16K_PG__ 1490 #define TTE_PGENTRIES (16384 >> TTE_SHIFT) /* number of ttes per page */ 1491 #else 1492 #define TTE_PGENTRIES (4096 >> TTE_SHIFT) /* number of ttes per page */ 1493 #endif 1494 1495 #define ARM_TTE_MAX (TTE_PGENTRIES) 1496 1497 #define ARM_TTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */ 1498 #define ARM_TTE_TYPE_FAULT 0x0000000000000000ULL /* unasigned - invalid entry */ 1499 1500 #define ARM_TTE_VALID 0x0000000000000001ULL /* valid entry */ 1501 1502 #define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */ 1503 #define ARM_TTE_TYPE_TABLE 0x0000000000000002ULL /* page table type */ 1504 #define ARM_TTE_TYPE_BLOCK 0x0000000000000000ULL /* block entry type */ 1505 #define ARM_TTE_TYPE_L3BLOCK 0x0000000000000002ULL 1506 #define ARM_TTE_TYPE_MASK 0x0000000000000002ULL /* mask for extracting the type */ 1507 1508 #ifdef __ARM_16K_PG__ 1509 /* 1510 * Note that L0/L1 block entries are disallowed for the 16KB granule size; what 1511 * are we doing with these? 1512 */ 1513 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 16KB L3 TTE entry */ 1514 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 128TB section */ 1515 #define ARM_TTE_BLOCK_L1_MASK 0x0000fff000000000ULL /* mask to extract phys address from L1 block entry */ 1516 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 64GB section */ 1517 #define ARM_TTE_BLOCK_L2_MASK 0x0000fffffe000000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 1518 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 32MB section */ 1519 #else 1520 #define ARM_TTE_BLOCK_SHIFT 12 /* entry shift for a 4KB L3 TTE entry */ 1521 #define ARM_TTE_BLOCK_L0_SHIFT ARM_TT_L0_SHIFT /* block shift for 2048GB section */ 1522 #define ARM_TTE_BLOCK_L1_MASK 0x0000ffffc0000000ULL /* mask to extract phys address from L1 block entry */ 1523 #define ARM_TTE_BLOCK_L1_SHIFT ARM_TT_L1_SHIFT /* block shift for 1GB section */ 1524 #define ARM_TTE_BLOCK_L2_MASK 0x0000ffffffe00000ULL /* mask to extract phys address from Level 2 Translation Block entry */ 1525 #define ARM_TTE_BLOCK_L2_SHIFT ARM_TT_L2_SHIFT /* block shift for 2MB section */ 1526 #endif 1527 1528 #define ARM_TTE_BLOCK_APSHIFT 6 1529 #define ARM_TTE_BLOCK_AP(x) ((x)<<ARM_TTE_BLOCK_APSHIFT) /* access protection */ 1530 #define ARM_TTE_BLOCK_APMASK (0x3 << ARM_TTE_BLOCK_APSHIFT) 1531 1532 #define ARM_TTE_BLOCK_ATTRINDX(x) ((x) << 2) /* memory attributes index */ 1533 #define ARM_TTE_BLOCK_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */ 1534 1535 #define ARM_TTE_BLOCK_SH(x) ((x) << 8) /* access shared */ 1536 #define ARM_TTE_BLOCK_SHMASK (0x3ULL << 8) /* mask access shared */ 1537 1538 #define ARM_TTE_BLOCK_AF 0x0000000000000400ULL /* value for access */ 1539 #define ARM_TTE_BLOCK_AFMASK 0x0000000000000400ULL /* access mask */ 1540 1541 #define ARM_TTE_BLOCK_NG 0x0000000000000800ULL /* value for a global mapping */ 1542 #define ARM_TTE_BLOCK_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 1543 1544 #define ARM_TTE_BLOCK_NS 0x0000000000000020ULL /* value for a secure mapping */ 1545 #define ARM_TTE_BLOCK_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 1546 1547 #define ARM_TTE_BLOCK_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 1548 #define ARM_TTE_BLOCK_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 1549 1550 #define ARM_TTE_BLOCK_NX 0x0040000000000000ULL /* value for no execute */ 1551 #define ARM_TTE_BLOCK_NXMASK 0x0040000000000000ULL /* no execute mask */ 1552 1553 #define ARM_TTE_BLOCK_WIRED 0x0400000000000000ULL /* value for software wired bit */ 1554 #define ARM_TTE_BLOCK_WIREDMASK 0x0400000000000000ULL /* software wired mask */ 1555 1556 #define ARM_TTE_BLOCK_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 1557 #define ARM_TTE_BLOCK_WRITEABLEMASK 0x0800000000000000ULL /* software writeable mask */ 1558 1559 #define ARM_TTE_TABLE_MASK 0x0000fffffffff000ULL /* mask for extracting pointer to next table (works at any level) */ 1560 1561 #define ARM_TTE_TABLE_APSHIFT 61 1562 #define ARM_TTE_TABLE_AP_NO_EFFECT 0x0ULL 1563 #define ARM_TTE_TABLE_AP_USER_NA 0x1ULL 1564 #define ARM_TTE_TABLE_AP_RO 0x2ULL 1565 #define ARM_TTE_TABLE_AP_KERN_RO 0x3ULL 1566 #define ARM_TTE_TABLE_AP(x) ((x) << ARM_TTE_TABLE_APSHIFT) /* access protection */ 1567 1568 #define ARM_TTE_TABLE_NS 0x8000000000000020ULL /* value for a secure mapping */ 1569 #define ARM_TTE_TABLE_NS_MASK 0x8000000000000020ULL /* notSecure mapping mask */ 1570 1571 #define ARM_TTE_TABLE_XN 0x1000000000000000ULL /* value for no execute */ 1572 #define ARM_TTE_TABLE_XNMASK 0x1000000000000000ULL /* no execute mask */ 1573 1574 #define ARM_TTE_TABLE_PXN 0x0800000000000000ULL /* value for privilege no execute bit */ 1575 #define ARM_TTE_TABLE_PXNMASK 0x0800000000000000ULL /* privilege execute mask */ 1576 1577 #if __ARM_KERNEL_PROTECT__ 1578 #define ARM_TTE_BOOT_BLOCK \ 1579 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 1580 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF | ARM_TTE_BLOCK_NG) 1581 #else /* __ARM_KERNEL_PROTECT__ */ 1582 #define ARM_TTE_BOOT_BLOCK \ 1583 (ARM_TTE_TYPE_BLOCK | ARM_TTE_VALID | ARM_TTE_BLOCK_SH(SH_OUTER_MEMORY) | \ 1584 ARM_TTE_BLOCK_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_TTE_BLOCK_AF) 1585 #endif /* __ARM_KERNEL_PROTECT__ */ 1586 1587 #define ARM_TTE_BOOT_TABLE (ARM_TTE_TYPE_TABLE | ARM_TTE_VALID ) 1588 /* 1589 * L3 Translation table 1590 * 1591 * 4KB granule size: 1592 * Each translation table is 4KB 1593 * 512 64-bit entries of 4KB (2^12) of address space. 1594 * Covers 2MB (2^21) of address space. 1595 * 1596 * 16KB granule size: 1597 * Each translation table is 16KB 1598 * 2048 64-bit entries of 16KB (2^14) of address space. 1599 * Covers 32MB (2^25) of address space. 1600 */ 1601 1602 #ifdef __ARM_16K_PG__ 1603 #define ARM_PTE_SIZE 0x0000000000004000ULL /* size of area covered by a tte */ 1604 #define ARM_PTE_OFFMASK 0x0000000000003fffULL /* offset within pte area */ 1605 #define ARM_PTE_SHIFT 14 /* page descriptor shift */ 1606 #define ARM_PTE_MASK 0x0000ffffffffc000ULL /* mask for output address in PTE */ 1607 #else 1608 #define ARM_PTE_SIZE 0x0000000000001000ULL /* size of area covered by a tte */ 1609 #define ARM_PTE_OFFMASK 0x0000000000000fffULL /* offset within pte area */ 1610 #define ARM_PTE_SHIFT 12 /* page descriptor shift */ 1611 #define ARM_PTE_MASK 0x0000fffffffff000ULL /* mask for output address in PTE */ 1612 #endif 1613 1614 #define ARM_TTE_PA_MASK 0x0000fffffffff000ULL 1615 1616 /* 1617 * L3 Page table entries 1618 * 1619 * The following page table entry types are possible: 1620 * 1621 * fault page entry 1622 * 63 2 0 1623 * +------------------------------+--+ 1624 * | ignored |00| 1625 * +------------------------------+--+ 1626 * 1627 * 1628 * 63 59 58 55 54 53 52 51 48 47 12 11 10 9 8 7 6 5 4 2 1 0 1629 * +-----+------+--+---+----+------+----------------------+--+--+----+----+--+-------+-+-+ 1630 * | ign |sw use|XN|PXN|HINT| zero | OutputAddress[47:12] |nG|AF| SH | AP |NS|AttrIdx|1|V| 1631 * +-----+------+--+---+----+------+----------------------+--+--+----+----+--+-------+-+-+ 1632 * 1633 * where: 1634 * nG: notGlobal bit 1635 * SH: Shareability field 1636 * AP: access protection 1637 * XN: eXecute Never bit 1638 * PXN: Privilege eXecute Never bit 1639 * NS: Non-Secure bit 1640 * HINT: 16 entry continuguous output hint 1641 * AttrIdx: Memory Attribute Index 1642 */ 1643 1644 #define PTE_SHIFT 3 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */ 1645 #ifdef __ARM_16K_PG__ 1646 #define PTE_PGENTRIES (16384 >> PTE_SHIFT) /* number of ptes per page */ 1647 #else 1648 #define PTE_PGENTRIES (4096 >> PTE_SHIFT) /* number of ptes per page */ 1649 #endif 1650 1651 #define ARM_PTE_EMPTY 0x0000000000000000ULL /* unassigned - invalid entry */ 1652 1653 /* markers for (invalid) PTE for a page sent to compressor */ 1654 #define ARM_PTE_COMPRESSED 0x8000000000000000ULL /* compressed... */ 1655 #define ARM_PTE_COMPRESSED_ALT 0x4000000000000000ULL /* ... and was "alt_acct" */ 1656 #define ARM_PTE_COMPRESSED_MASK 0xC000000000000000ULL 1657 1658 #define ARM_PTE_TYPE 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */ 1659 #define ARM_PTE_TYPE_VALID 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */ 1660 #define ARM_PTE_TYPE_FAULT 0x0000000000000000ULL /* invalid L3 entry */ 1661 #define ARM_PTE_TYPE_MASK 0x0000000000000002ULL /* mask to get pte type */ 1662 1663 /* This mask works for both 16K and 4K pages because bits 12-13 will be zero in 16K pages */ 1664 #define ARM_PTE_PAGE_MASK 0x0000FFFFFFFFF000ULL /* output address mask for page */ 1665 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for the output address in the entry */ 1666 1667 #define ARM_PTE_AP(x) ((x) << 6) /* access protections */ 1668 #define ARM_PTE_APMASK (0x3ULL << 6) /* mask access protections */ 1669 #define ARM_PTE_EXTRACT_AP(x) (((x) >> 6) & 0x3ULL) /* extract access protections from PTE */ 1670 1671 #define ARM_PTE_ATTRINDX(x) ((x) << 2) /* memory attributes index */ 1672 #define ARM_PTE_ATTRINDXMASK (0x7ULL << 2) /* mask memory attributes index */ 1673 #define ARM_PTE_EXTRACT_ATTRINDX(x) (((x) >> 2) & 0x7ULL) /* extract memory attributes index */ 1674 1675 #define ARM_PTE_SH(x) ((x) << 8) /* access shared */ 1676 #define ARM_PTE_SHMASK (0x3ULL << 8) /* mask access shared */ 1677 1678 #define ARM_PTE_AF 0x0000000000000400ULL /* value for access */ 1679 #define ARM_PTE_AFMASK 0x0000000000000400ULL /* access mask */ 1680 1681 #define ARM_PTE_NG 0x0000000000000800ULL /* value for a global mapping */ 1682 #define ARM_PTE_NG_MASK 0x0000000000000800ULL /* notGlobal mapping mask */ 1683 1684 #define ARM_PTE_NS 0x0000000000000020ULL /* value for a secure mapping */ 1685 #define ARM_PTE_NS_MASK 0x0000000000000020ULL /* notSecure mapping mask */ 1686 1687 #define ARM_PTE_HINT 0x0010000000000000ULL /* value for contiguous entries hint */ 1688 #define ARM_PTE_HINT_MASK 0x0010000000000000ULL /* mask for contiguous entries hint */ 1689 1690 #if __ARM_16K_PG__ 1691 #define ARM_PTE_HINT_ENTRIES 128ULL /* number of entries the hint covers */ 1692 #define ARM_PTE_HINT_ENTRIES_SHIFT 7ULL /* shift to construct the number of entries */ 1693 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFE00000ULL /* mask to extract the starting hint address */ 1694 #define ARM_PTE_HINT_ADDR_SHIFT 21 /* shift for the hint address */ 1695 #define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFE00000ULL /* mask to extract the starting hint address */ 1696 #else 1697 #define ARM_PTE_HINT_ENTRIES 16ULL /* number of entries the hint covers */ 1698 #define ARM_PTE_HINT_ENTRIES_SHIFT 4ULL /* shift to construct the number of entries */ 1699 #define ARM_PTE_HINT_ADDR_MASK 0x0000FFFFFFFF0000ULL /* mask to extract the starting hint address */ 1700 #define ARM_PTE_HINT_ADDR_SHIFT 16 /* shift for the hint address */ 1701 #define ARM_KVA_HINT_ADDR_MASK 0xFFFFFFFFFFFF0000ULL /* mask to extract the starting hint address */ 1702 #endif 1703 1704 #define ARM_PTE_PNX 0x0020000000000000ULL /* value for privilege no execute bit */ 1705 #define ARM_PTE_PNXMASK 0x0020000000000000ULL /* privilege no execute mask */ 1706 1707 #define ARM_PTE_NX 0x0040000000000000ULL /* value for no execute bit */ 1708 #define ARM_PTE_NXMASK 0x0040000000000000ULL /* no execute mask */ 1709 1710 #define ARM_PTE_XMASK (ARM_PTE_PNXMASK | ARM_PTE_NXMASK) 1711 1712 #define ARM_PTE_WIRED 0x0400000000000000ULL /* value for software wired bit */ 1713 #define ARM_PTE_WIRED_MASK 0x0400000000000000ULL /* software wired mask */ 1714 1715 #define ARM_PTE_WRITEABLE 0x0800000000000000ULL /* value for software writeable bit */ 1716 #define ARM_PTE_WRITEABLE_MASK 0x0800000000000000ULL /* software writeable mask */ 1717 1718 #define ARM_PTE_BOOT_PAGE_BASE \ 1719 (ARM_PTE_TYPE_VALID | ARM_PTE_SH(SH_OUTER_MEMORY) | \ 1720 ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) | ARM_PTE_AF) 1721 1722 #if __ARM_KERNEL_PROTECT__ 1723 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE | ARM_PTE_NG) 1724 #else /* __ARM_KERNEL_PROTECT__ */ 1725 #define ARM_PTE_BOOT_PAGE (ARM_PTE_BOOT_PAGE_BASE) 1726 #endif /* __ARM_KERNEL_PROTECT__ */ 1727 1728 /* 1729 * TLBI appers to only deal in 4KB page addresses, so give 1730 * it an explicit shift of 12. 1731 */ 1732 #define TLBI_ADDR_SHIFT (0) 1733 #define TLBI_ADDR_SIZE (44) 1734 #define TLBI_ADDR_MASK ((1ULL << TLBI_ADDR_SIZE) - 1) 1735 #define TLBI_ASID_SHIFT (48) 1736 #define TLBI_ASID_SIZE (16) 1737 #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1)) 1738 1739 #define RTLBI_ADDR_SIZE (37) 1740 #define RTLBI_ADDR_MASK ((1ULL << RTLBI_ADDR_SIZE) - 1) 1741 #define RTLBI_ADDR_SHIFT ARM_TT_L3_SHIFT 1742 #define RTLBI_TG(_page_shift_) ((uint64_t)((((_page_shift_) - 12) >> 1) + 1) << 46) 1743 #define RTLBI_SCALE_SHIFT (44) 1744 #define RTLBI_NUM_SHIFT (39) 1745 1746 /* 1747 * Exception Syndrome Register 1748 * 1749 * 31 26 25 24 0 1750 * +------+--+------------------+ 1751 * | EC |IL| ISS | 1752 * +------+--+------------------+ 1753 * 1754 * EC - Exception Class 1755 * IL - Instruction Length 1756 * ISS - Instruction Specific Syndrome 1757 * 1758 * Note: The ISS can have many forms. These are defined separately below. 1759 */ 1760 1761 #define ESR_EC_SHIFT 26 1762 #define ESR_EC_MASK (0x3FULL << ESR_EC_SHIFT) 1763 #define ESR_EC(x) ((x & ESR_EC_MASK) >> ESR_EC_SHIFT) 1764 1765 #define ESR_IL_SHIFT 25 1766 #define ESR_IL (1 << ESR_IL_SHIFT) 1767 1768 #define ESR_INSTR_IS_2BYTES(x) (!(x & ESR_IL)) 1769 1770 #define ESR_ISS_MASK 0x01FFFFFF 1771 #define ESR_ISS(x) (x & ESR_ISS_MASK) 1772 1773 #ifdef __ASSEMBLER__ 1774 /* Define only the classes we need to test in the exception vectors. */ 1775 #define ESR_EC_IABORT_EL1 0x21 1776 #define ESR_EC_DABORT_EL1 0x25 1777 #define ESR_EC_SP_ALIGN 0x26 1778 #else 1779 typedef enum { 1780 ESR_EC_UNCATEGORIZED = 0x00, 1781 ESR_EC_WFI_WFE = 0x01, 1782 ESR_EC_MCR_MRC_CP15_TRAP = 0x03, 1783 ESR_EC_MCRR_MRRC_CP15_TRAP = 0x04, 1784 ESR_EC_MCR_MRC_CP14_TRAP = 0x05, 1785 ESR_EC_LDC_STC_CP14_TRAP = 0x06, 1786 ESR_EC_TRAP_SIMD_FP = 0x07, 1787 ESR_EC_PTRAUTH_INSTR_TRAP = 0x09, 1788 ESR_EC_MCRR_MRRC_CP14_TRAP = 0x0c, 1789 ESR_EC_ILLEGAL_INSTR_SET = 0x0e, 1790 ESR_EC_SVC_32 = 0x11, 1791 ESR_EC_HVC_32 = 0x12, 1792 ESR_EC_SVC_64 = 0x15, 1793 ESR_EC_HVC_64 = 0x16, 1794 ESR_EC_MSR_TRAP = 0x18, 1795 #if __has_feature(ptrauth_calls) 1796 ESR_EC_PAC_FAIL = 0x1C, 1797 #endif /* __has_feature(ptrauth_calls) */ 1798 ESR_EC_IABORT_EL0 = 0x20, 1799 ESR_EC_IABORT_EL1 = 0x21, 1800 ESR_EC_PC_ALIGN = 0x22, 1801 ESR_EC_DABORT_EL0 = 0x24, 1802 ESR_EC_DABORT_EL1 = 0x25, 1803 ESR_EC_SP_ALIGN = 0x26, 1804 ESR_EC_FLOATING_POINT_32 = 0x28, 1805 ESR_EC_FLOATING_POINT_64 = 0x2C, 1806 ESR_EC_SERROR_INTERRUPT = 0x2F, 1807 ESR_EC_BKPT_REG_MATCH_EL0 = 0x30, // Breakpoint Debug event taken to the EL from a lower EL. 1808 ESR_EC_BKPT_REG_MATCH_EL1 = 0x31, // Breakpoint Debug event taken to the EL from the EL. 1809 ESR_EC_SW_STEP_DEBUG_EL0 = 0x32, // Software Step Debug event taken to the EL from a lower EL. 1810 ESR_EC_SW_STEP_DEBUG_EL1 = 0x33, // Software Step Debug event taken to the EL from the EL. 1811 ESR_EC_WATCHPT_MATCH_EL0 = 0x34, // Watchpoint Debug event taken to the EL from a lower EL. 1812 ESR_EC_WATCHPT_MATCH_EL1 = 0x35, // Watchpoint Debug event taken to the EL from the EL. 1813 ESR_EC_BKPT_AARCH32 = 0x38, 1814 ESR_EC_BRK_AARCH64 = 0x3C, 1815 } esr_exception_class_t; 1816 1817 typedef enum { 1818 FSC_TRANSLATION_FAULT_L0 = 0x04, 1819 FSC_TRANSLATION_FAULT_L1 = 0x05, 1820 FSC_TRANSLATION_FAULT_L2 = 0x06, 1821 FSC_TRANSLATION_FAULT_L3 = 0x07, 1822 FSC_ACCESS_FLAG_FAULT_L1 = 0x09, 1823 FSC_ACCESS_FLAG_FAULT_L2 = 0x0A, 1824 FSC_ACCESS_FLAG_FAULT_L3 = 0x0B, 1825 FSC_PERMISSION_FAULT_L1 = 0x0D, 1826 FSC_PERMISSION_FAULT_L2 = 0x0E, 1827 FSC_PERMISSION_FAULT_L3 = 0x0F, 1828 FSC_SYNC_EXT_ABORT = 0x10, 1829 FSC_SYNC_EXT_ABORT_TT_L1 = 0x15, 1830 FSC_SYNC_EXT_ABORT_TT_L2 = 0x16, 1831 FSC_SYNC_EXT_ABORT_TT_L3 = 0x17, 1832 FSC_SYNC_PARITY = 0x18, 1833 FSC_ASYNC_PARITY = 0x19, 1834 FSC_SYNC_PARITY_TT_L1 = 0x1D, 1835 FSC_SYNC_PARITY_TT_L2 = 0x1E, 1836 FSC_SYNC_PARITY_TT_L3 = 0x1F, 1837 FSC_ALIGNMENT_FAULT = 0x21, 1838 FSC_DEBUG_FAULT = 0x22, 1839 } fault_status_t; 1840 #endif /* ASSEMBLER */ 1841 1842 /* 1843 * HVC event 1844 * 24 16 15 0 1845 * +---------+-----+ 1846 * |000000000| IMM | 1847 * +---------+-----+ 1848 * 1849 * where: 1850 * IMM: Immediate value 1851 */ 1852 1853 #define ISS_HVC_IMM_MASK 0xffff 1854 #define ISS_HVC_IMM(x) ((x) & ISS_HVC_IMM_MASK) 1855 1856 /* 1857 * Software step debug event ISS (EL1) 1858 * 24 23 6 5 0 1859 * +---+-----------------+--+------+ 1860 * |ISV|00000000000000000|EX| IFSC | 1861 * +---+-----------------+--+------+ 1862 * 1863 * where: 1864 * ISV: Instruction syndrome valid 1865 * EX: Exclusive access 1866 * IFSC: Instruction Fault Status Code 1867 */ 1868 1869 #define ISS_SSDE_ISV_SHIFT 24 1870 #define ISS_SSDE_ISV (0x1 << ISS_SSDE_ISV_SHIFT) 1871 1872 #define ISS_SSDE_EX_SHIFT 6 1873 #define ISS_SSDE_EX (0x1 << ISS_SSDE_EX_SHIFT) 1874 1875 #define ISS_SSDE_FSC_MASK 0x3F 1876 #define ISS_SSDE_FSC(x) (x & ISS_SSDE_FSC_MASK) 1877 1878 /* 1879 * Instruction Abort ISS (EL1) 1880 * 24 10 9 5 0 1881 * +--------------+---+--+---+------+ 1882 * |00000000000000|FnV|EA|000| IFSC | 1883 * +--------------+---+--+---+------+ 1884 * 1885 * where: 1886 * FnV: FAR not Valid 1887 * EA: External Abort type 1888 * IFSC: Instruction Fault Status Code 1889 */ 1890 1891 #define ISS_IA_FNV_SHIFT 10 1892 #define ISS_IA_FNV (0x1 << ISS_IA_FNV_SHIFT) 1893 1894 #define ISS_IA_EA_SHIFT 9 1895 #define ISS_IA_EA (0x1 << ISS_IA_EA_SHIFT) 1896 1897 #define ISS_IA_FSC_MASK 0x3F 1898 #define ISS_IA_FSC(x) (x & ISS_IA_FSC_MASK) 1899 1900 1901 /* 1902 * Data Abort ISS (EL1) 1903 * 1904 * 24 10 9 8 7 6 5 0 1905 * +--------------+---+--+--+-----+---+----+ 1906 * |00000000000000|FnV|EA|CM|S1PTW|WnR|DFSC| 1907 * +--------------+---+--+--+-----+---+----+ 1908 * 1909 * where: 1910 * FnV: FAR not Valid 1911 * EA: External Abort type 1912 * CM: Cache Maintenance operation 1913 * WnR: Write not Read 1914 * S1PTW: Stage 2 exception on Stage 1 page table walk 1915 * DFSC: Data Fault Status Code 1916 */ 1917 #define ISS_DA_FNV_SHIFT 10 1918 #define ISS_DA_FNV (0x1 << ISS_DA_FNV_SHIFT) 1919 1920 #define ISS_DA_EA_SHIFT 9 1921 #define ISS_DA_EA (0x1 << ISS_DA_EA_SHIFT) 1922 1923 #define ISS_DA_CM_SHIFT 8 1924 #define ISS_DA_CM (0x1 << ISS_DA_CM_SHIFT) 1925 1926 #define ISS_DA_WNR_SHIFT 6 1927 #define ISS_DA_WNR (0x1 << ISS_DA_WNR_SHIFT) 1928 1929 #define ISS_DA_S1PTW_SHIFT 7 1930 #define ISS_DA_S1PTW (0x1 << ISS_DA_S1PTW_SHIFT) 1931 1932 #define ISS_DA_FSC_MASK 0x3F 1933 #define ISS_DA_FSC(x) (x & ISS_DA_FSC_MASK) 1934 1935 /* 1936 * Floating Point Exception ISS (EL1) 1937 * 1938 * 24 23 22 8 7 4 3 2 1 0 1939 * +-+---+---------------+---+--+---+---+---+---+---+ 1940 * |0|TFV|000000000000000|IDF|00|IXF|UFF|OFF|DZF|IOF| 1941 * +-+---+---------------+---+--+---+---+---+---+---+ 1942 * 1943 * where: 1944 * TFV: Trapped Fault Valid 1945 * IDF: Input Denormal Exception 1946 * IXF: Input Inexact Exception 1947 * UFF: Underflow Exception 1948 * OFF: Overflow Exception 1949 * DZF: Divide by Zero Exception 1950 * IOF: Invalid Operation Exception 1951 */ 1952 #define ISS_FP_TFV_SHIFT 23 1953 #define ISS_FP_TFV (0x1 << ISS_FP_TFV_SHIFT) 1954 1955 #define ISS_FP_IDF_SHIFT 7 1956 #define ISS_FP_IDF (0x1 << ISS_FP_IDF_SHIFT) 1957 1958 #define ISS_FP_IXF_SHIFT 4 1959 #define ISS_FP_IXF (0x1 << ISS_FP_IXF_SHIFT) 1960 1961 #define ISS_FP_UFF_SHIFT 3 1962 #define ISS_FP_UFF (0x1 << ISS_FP_UFF_SHIFT) 1963 1964 #define ISS_FP_OFF_SHIFT 2 1965 #define ISS_FP_OFF (0x1 << ISS_FP_OFF_SHIFT) 1966 1967 #define ISS_FP_DZF_SHIFT 1 1968 #define ISS_FP_DZF (0x1 << ISS_FP_DZF_SHIFT) 1969 1970 #define ISS_FP_IOF_SHIFT 0 1971 #define ISS_FP_IOF (0x1 << ISS_FP_IOF_SHIFT) 1972 1973 /* 1974 * Breakpoint Exception ISS (EL1) 1975 * 24 16 0 1976 * +---------+---------+ 1977 * |000000000| Comment | 1978 * +---------+---------+ 1979 * 1980 * where: 1981 * Comment: Instruction Comment Field Value 1982 */ 1983 #define ISS_BRK_COMMENT_MASK 0xFFFF 1984 #define ISS_BRK_COMMENT(x) (x & ISS_BRK_COMMENT_MASK) 1985 1986 1987 #if HAS_UCNORMAL_MEM 1988 #define ISS_UC 0x11 1989 #endif /* HAS_UCNORMAL_MEM */ 1990 1991 1992 1993 1994 /* 1995 * Physical Address Register (EL1) 1996 */ 1997 #define PAR_F_SHIFT 0 1998 #define PAR_F (0x1 << PAR_F_SHIFT) 1999 2000 #define PLATFORM_SYSCALL_TRAP_NO 0x80000000 2001 2002 #define ARM64_SYSCALL_CODE_REG_NUM (16) 2003 2004 #define ARM64_CLINE_SHIFT 6 2005 2006 #if defined(APPLE_ARM64_ARCH_FAMILY) 2007 #define L2CERRSTS_DATSBEESV (1ULL << 2) /* L2C data single bit ECC error */ 2008 #define L2CERRSTS_DATDBEESV (1ULL << 4) /* L2C data double bit ECC error */ 2009 #endif 2010 2011 /* 2012 * Timer definitions. 2013 */ 2014 #define CNTKCTL_EL1_PL0PTEN (0x1 << 9) /* 1: EL0 access to physical timer regs permitted */ 2015 #define CNTKCTL_EL1_PL0VTEN (0x1 << 8) /* 1: EL0 access to virtual timer regs permitted */ 2016 #define CNTKCTL_EL1_EVENTI_MASK (0x000000f0) /* Mask for bits describing which bit to use for triggering event stream */ 2017 #define CNTKCTL_EL1_EVENTI_SHIFT (0x4) /* Shift for same */ 2018 #define CNTKCTL_EL1_EVENTDIR (0x1 << 3) /* 1: one-to-zero transition of specified bit causes event */ 2019 #define CNTKCTL_EL1_EVNTEN (0x1 << 2) /* 1: enable event stream */ 2020 #define CNTKCTL_EL1_PL0VCTEN (0x1 << 1) /* 1: EL0 access to virtual timebase + frequency reg enabled */ 2021 #define CNTKCTL_EL1_PL0PCTEN (0x1 << 0) /* 1: EL0 access to physical timebase + frequency reg enabled */ 2022 2023 #define CNTV_CTL_EL0_ISTATUS (0x1 << 2) /* (read only): whether interrupt asserted */ 2024 #define CNTV_CTL_EL0_IMASKED (0x1 << 1) /* 1: interrupt masked */ 2025 #define CNTV_CTL_EL0_ENABLE (0x1 << 0) /* 1: virtual timer enabled */ 2026 2027 #define CNTP_CTL_EL0_ISTATUS CNTV_CTL_EL0_ISTATUS 2028 #define CNTP_CTL_EL0_IMASKED CNTV_CTL_EL0_IMASKED 2029 #define CNTP_CTL_EL0_ENABLE CNTV_CTL_EL0_ENABLE 2030 2031 #define MIDR_EL1_REV_SHIFT 0 2032 #define MIDR_EL1_REV_MASK (0xf << MIDR_EL1_REV_SHIFT) 2033 #define MIDR_EL1_PNUM_SHIFT 4 2034 #define MIDR_EL1_PNUM_MASK (0xfff << MIDR_EL1_PNUM_SHIFT) 2035 #define MIDR_EL1_ARCH_SHIFT 16 2036 #define MIDR_EL1_ARCH_MASK (0xf << MIDR_EL1_ARCH_SHIFT) 2037 #define MIDR_EL1_VAR_SHIFT 20 2038 #define MIDR_EL1_VAR_MASK (0xf << MIDR_EL1_VAR_SHIFT) 2039 #define MIDR_EL1_IMP_SHIFT 24 2040 #define MIDR_EL1_IMP_MASK (0xff << MIDR_EL1_IMP_SHIFT) 2041 2042 #define MIDR_FIJI (0x002 << MIDR_EL1_PNUM_SHIFT) 2043 #define MIDR_CAPRI (0x003 << MIDR_EL1_PNUM_SHIFT) 2044 #define MIDR_MAUI (0x004 << MIDR_EL1_PNUM_SHIFT) 2045 #define MIDR_ELBA (0x005 << MIDR_EL1_PNUM_SHIFT) 2046 #define MIDR_CAYMAN (0x006 << MIDR_EL1_PNUM_SHIFT) 2047 #define MIDR_MYST (0x007 << MIDR_EL1_PNUM_SHIFT) 2048 #define MIDR_SKYE_MONSOON (0x008 << MIDR_EL1_PNUM_SHIFT) 2049 #define MIDR_SKYE_MISTRAL (0x009 << MIDR_EL1_PNUM_SHIFT) 2050 #define MIDR_CYPRUS_VORTEX (0x00B << MIDR_EL1_PNUM_SHIFT) 2051 #define MIDR_CYPRUS_TEMPEST (0x00C << MIDR_EL1_PNUM_SHIFT) 2052 #define MIDR_M9 (0x00F << MIDR_EL1_PNUM_SHIFT) 2053 #define MIDR_ARUBA_VORTEX (0x010 << MIDR_EL1_PNUM_SHIFT) 2054 #define MIDR_ARUBA_TEMPEST (0x011 << MIDR_EL1_PNUM_SHIFT) 2055 2056 #ifdef APPLELIGHTNING 2057 #define MIDR_CEBU_LIGHTNING (0x012 << MIDR_EL1_PNUM_SHIFT) 2058 #define MIDR_CEBU_THUNDER (0x013 << MIDR_EL1_PNUM_SHIFT) 2059 #define MIDR_TURKS (0x026 << MIDR_EL1_PNUM_SHIFT) 2060 #endif 2061 2062 #ifdef APPLEFIRESTORM 2063 #define MIDR_SICILY_ICESTORM (0x020 << MIDR_EL1_PNUM_SHIFT) 2064 #define MIDR_SICILY_FIRESTORM (0x021 << MIDR_EL1_PNUM_SHIFT) 2065 #define MIDR_TONGA_ICESTORM (0x022 << MIDR_EL1_PNUM_SHIFT) 2066 #define MIDR_TONGA_FIRESTORM (0x023 << MIDR_EL1_PNUM_SHIFT) 2067 #define MIDR_JADE_CHOP_ICESTORM (0x024 << MIDR_EL1_PNUM_SHIFT) 2068 #define MIDR_JADE_CHOP_FIRESTORM (0x025 << MIDR_EL1_PNUM_SHIFT) 2069 #define MIDR_JADE_DIE_ICESTORM (0x028 << MIDR_EL1_PNUM_SHIFT) 2070 #define MIDR_JADE_DIE_FIRESTORM (0x029 << MIDR_EL1_PNUM_SHIFT) 2071 #endif 2072 2073 2074 2075 2076 2077 /* 2078 * Apple-ISA-Extensions ID Register. 2079 */ 2080 #define AIDR_MUL53 (1 << 0) 2081 #define AIDR_WKDM (1 << 1) 2082 #define AIDR_ARCHRETENTION (1 << 2) 2083 2084 2085 2086 /* 2087 * CoreSight debug registers 2088 */ 2089 #define CORESIGHT_ED 0 2090 #define CORESIGHT_CTI 1 2091 #define CORESIGHT_PMU 2 2092 #define CORESIGHT_UTT 3 /* Not truly a coresight thing, but at a fixed convenient location right after the coresight region */ 2093 2094 #define CORESIGHT_OFFSET(x) ((x) * 0x10000) 2095 #define CORESIGHT_REGIONS 4 2096 #define CORESIGHT_SIZE 0x1000 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 /* 2108 * ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 2109 * 2110 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2111 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2112 * | rndr | tlb | ts | fhm | dp | sm4 | sm3 | sha3 | rdm | res0 | atomic | crc32 | sha2 | sha1 | aes | res0 | 2113 * +--------+-------+------+-------+------+-------+-------+------+-------+--------+--------+-------+------+------+-----+------+ 2114 */ 2115 2116 #define ID_AA64ISAR0_EL1_TS_OFFSET 52 2117 #define ID_AA64ISAR0_EL1_TS_MASK (0xfull << ID_AA64ISAR0_EL1_TS_OFFSET) 2118 #define ID_AA64ISAR0_EL1_TS_FLAGM_EN (1ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2119 #define ID_AA64ISAR0_EL1_TS_FLAGM2_EN (2ull << ID_AA64ISAR0_EL1_TS_OFFSET) 2120 2121 #define ID_AA64ISAR0_EL1_FHM_OFFSET 48 2122 #define ID_AA64ISAR0_EL1_FHM_MASK (0xfull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2123 #define ID_AA64ISAR0_EL1_FHM_8_2 (1ull << ID_AA64ISAR0_EL1_FHM_OFFSET) 2124 2125 #define ID_AA64ISAR0_EL1_DP_OFFSET 44 2126 #define ID_AA64ISAR0_EL1_DP_MASK (0xfull << ID_AA64ISAR0_EL1_DP_OFFSET) 2127 #define ID_AA64ISAR0_EL1_DP_EN (1ull << ID_AA64ISAR0_EL1_DP_OFFSET) 2128 2129 #define ID_AA64ISAR0_EL1_SHA3_OFFSET 32 2130 #define ID_AA64ISAR0_EL1_SHA3_MASK (0xfull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2131 #define ID_AA64ISAR0_EL1_SHA3_EN (1ull << ID_AA64ISAR0_EL1_SHA3_OFFSET) 2132 2133 #define ID_AA64ISAR0_EL1_RDM_OFFSET 28 2134 #define ID_AA64ISAR0_EL1_RDM_MASK (0xfull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2135 #define ID_AA64ISAR0_EL1_RDM_EN (1ull << ID_AA64ISAR0_EL1_RDM_OFFSET) 2136 2137 #define ID_AA64ISAR0_EL1_ATOMIC_OFFSET 20 2138 #define ID_AA64ISAR0_EL1_ATOMIC_MASK (0xfull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2139 #define ID_AA64ISAR0_EL1_ATOMIC_8_1 (2ull << ID_AA64ISAR0_EL1_ATOMIC_OFFSET) 2140 2141 #define ID_AA64ISAR0_EL1_CRC32_OFFSET 16 2142 #define ID_AA64ISAR0_EL1_CRC32_MASK (0xfull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2143 #define ID_AA64ISAR0_EL1_CRC32_EN (1ull << ID_AA64ISAR0_EL1_CRC32_OFFSET) 2144 2145 #define ID_AA64ISAR0_EL1_SHA2_OFFSET 12 2146 #define ID_AA64ISAR0_EL1_SHA2_MASK (0xfull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2147 #define ID_AA64ISAR0_EL1_SHA2_EN (1ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2148 #define ID_AA64ISAR0_EL1_SHA2_512_EN (2ull << ID_AA64ISAR0_EL1_SHA2_OFFSET) 2149 2150 #define ID_AA64ISAR0_EL1_SHA1_OFFSET 8 2151 #define ID_AA64ISAR0_EL1_SHA1_MASK (0xfull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2152 #define ID_AA64ISAR0_EL1_SHA1_EN (1ull << ID_AA64ISAR0_EL1_SHA1_OFFSET) 2153 2154 #define ID_AA64ISAR0_EL1_AES_OFFSET 4 2155 #define ID_AA64ISAR0_EL1_AES_MASK (0xfull << ID_AA64ISAR0_EL1_AES_OFFSET) 2156 #define ID_AA64ISAR0_EL1_AES_EN (1ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2157 #define ID_AA64ISAR0_EL1_AES_PMULL_EN (2ull << ID_AA64ISAR0_EL1_AES_OFFSET) 2158 2159 /* 2160 * ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 1 2161 * 2162 * 63 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2163 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2164 * | res0 | i8mm | dgh | bf16 | specres | sb | frintts | gpi | gpa | lrcpc | fcma | jscvt | api | apa | dpb | 2165 * +------+------+-----+------+---------+------+---------+-----+-----+-------+------+-------+-----+-----+-----+ 2166 */ 2167 2168 #define ID_AA64ISAR1_EL1_I8MM_OFFSET 52 2169 #define ID_AA64ISAR1_EL1_I8MM_MASK (0xfull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2170 #define ID_AA64ISAR1_EL1_I8MM_EN (1ull << ID_AA64ISAR1_EL1_I8MM_OFFSET) 2171 2172 #define ID_AA64ISAR1_EL1_DGH_OFFSET 48 2173 #define ID_AA64ISAR1_EL1_DGH_MASK (0xfull << ID_AA64ISAR1_EL1_DGH_OFFSET) 2174 2175 #define ID_AA64ISAR1_EL1_BF16_OFFSET 44 2176 #define ID_AA64ISAR1_EL1_BF16_MASK (0xfull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2177 #define ID_AA64ISAR1_EL1_BF16_EN (1ull << ID_AA64ISAR1_EL1_BF16_OFFSET) 2178 2179 #define ID_AA64ISAR1_EL1_SPECRES_OFFSET 40 2180 #define ID_AA64ISAR1_EL1_SPECRES_MASK (0xfull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2181 #define ID_AA64ISAR1_EL1_SPECRES_EN (1ull << ID_AA64ISAR1_EL1_SPECRES_OFFSET) 2182 2183 #define ID_AA64ISAR1_EL1_SB_OFFSET 36 2184 #define ID_AA64ISAR1_EL1_SB_MASK (0xfull << ID_AA64ISAR1_EL1_SB_OFFSET) 2185 #define ID_AA64ISAR1_EL1_SB_EN (1ull << ID_AA64ISAR1_EL1_SB_OFFSET) 2186 2187 #define ID_AA64ISAR1_EL1_FRINTTS_OFFSET 32 2188 #define ID_AA64ISAR1_EL1_FRINTTS_MASK (0xfull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 2189 #define ID_AA64ISAR1_EL1_FRINTTS_EN (1ull << ID_AA64ISAR1_EL1_FRINTTS_OFFSET) 2190 2191 #define ID_AA64ISAR1_EL1_GPI_OFFSET 28 2192 #define ID_AA64ISAR1_EL1_GPI_MASK (0xfull << ID_AA64ISAR1_EL1_GPI_OFFSET) 2193 #define ID_AA64ISAR1_EL1_GPI_EN (1ull << ID_AA64ISAR1_EL1_GPI_OFFSET) 2194 2195 #define ID_AA64ISAR1_EL1_GPA_OFFSET 24 2196 #define ID_AA64ISAR1_EL1_GPA_MASK (0xfull << ID_AA64ISAR1_EL1_GPA_OFFSET) 2197 2198 #define ID_AA64ISAR1_EL1_LRCPC_OFFSET 20 2199 #define ID_AA64ISAR1_EL1_LRCPC_MASK (0xfull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2200 #define ID_AA64ISAR1_EL1_LRCPC_EN (1ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2201 #define ID_AA64ISAR1_EL1_LRCP2C_EN (2ull << ID_AA64ISAR1_EL1_LRCPC_OFFSET) 2202 2203 #define ID_AA64ISAR1_EL1_FCMA_OFFSET 16 2204 #define ID_AA64ISAR1_EL1_FCMA_MASK (0xfull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 2205 #define ID_AA64ISAR1_EL1_FCMA_EN (1ull << ID_AA64ISAR1_EL1_FCMA_OFFSET) 2206 2207 #define ID_AA64ISAR1_EL1_JSCVT_OFFSET 12 2208 #define ID_AA64ISAR1_EL1_JSCVT_MASK (0xfull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 2209 #define ID_AA64ISAR1_EL1_JSCVT_EN (1ull << ID_AA64ISAR1_EL1_JSCVT_OFFSET) 2210 2211 #define ID_AA64ISAR1_EL1_API_OFFSET 8 2212 #define ID_AA64ISAR1_EL1_API_MASK (0xfull << ID_AA64ISAR1_EL1_API_OFFSET) 2213 #define ID_AA64ISAR1_EL1_API_PAuth_EN (1ull << ID_AA64ISAR1_EL1_API_OFFSET) 2214 #define ID_AA64ISAR1_EL1_API_PAuth2_EN (3ull << ID_AA64ISAR1_EL1_API_OFFSET) 2215 #define ID_AA64ISAR1_EL1_API_FPAC_EN (4ull << ID_AA64ISAR1_EL1_API_OFFSET) 2216 2217 #define ID_AA64ISAR1_EL1_APA_OFFSET 4 2218 #define ID_AA64ISAR1_EL1_APA_MASK (0xfull << ID_AA64ISAR1_EL1_APA_OFFSET) 2219 2220 #define ID_AA64ISAR1_EL1_DPB_OFFSET 0 2221 #define ID_AA64ISAR1_EL1_DPB_MASK (0xfull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2222 #define ID_AA64ISAR1_EL1_DPB_EN (1ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2223 #define ID_AA64ISAR1_EL1_DPB2_EN (2ull << ID_AA64ISAR1_EL1_DPB_OFFSET) 2224 2225 /* 2226 * ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 2 2227 * 2228 * 63 8 7 4 3 0 2229 * +------+-------+------+ 2230 * | res0 | RPRES | WFxT | 2231 * +------+-------+------+ 2232 */ 2233 2234 #define ID_AA64ISAR2_EL1_RPRES_OFFSET 4 2235 #define ID_AA64ISAR2_EL1_RPRES_MASK (0xfull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 2236 #define ID_AA64ISAR2_EL1_RPRES_EN (1ull << ID_AA64ISAR2_EL1_RPRES_OFFSET) 2237 2238 #define ID_AA64ISAR2_EL1_WFxT_OFFSET 0 2239 #define ID_AA64ISAR2_EL1_WFxT_MASK (0xfull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 2240 #define ID_AA64ISAR2_EL1_WFxT_EN (1ull << ID_AA64ISAR2_EL1_WFxT_OFFSET) 2241 2242 /* 2243 * ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0 2244 * 63 60 59 56 55 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2245 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 2246 * | ECV | FGT | RES0 | ExS | TGran4_2 | TGran64_2 | TGran16_2 | TGran4 | TGran64 | TGran16 | BigEndEL0 | SNSMem | BigEnd | ASIDBits | PARange | 2247 * +-------+-------+------------+-------+----------+-----------+-----------+--------+---------+---------+-----------+--------+--------+----------+---------+ 2248 */ 2249 2250 #define ID_AA64MMFR0_EL1_ECV_OFFSET 60 2251 #define ID_AA64MMFR0_EL1_ECV_MASK (0xfull << ID_AA64MMFR0_EL1_ECV_OFFSET) 2252 #define ID_AA64MMFR0_EL1_ECV_EN (1ull << ID_AA64MMFR0_EL1_ECV_OFFSET) 2253 2254 /* 2255 * ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2 2256 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 14 8 7 4 3 0 2257 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 2258 * | E0PD | EVT | BBM | TTL | RES0 | FWB | IDS | AT | ST | NV | CCIDX | VARANGE | IESB | LSM | UAO | CnP | 2259 * +------+-------+-------+-------+--------+-------+-------+------+------+------+-------+---------+------+-------+-------+-------+ 2260 */ 2261 2262 #define ID_AA64MMFR2_EL1_AT_OFFSET 32 2263 #define ID_AA64MMFR2_EL1_AT_MASK (0xfull << ID_AA64MMFR2_EL1_AT_OFFSET) 2264 #define ID_AA64MMFR2_EL1_AT_LSE2_EN (1ull << ID_AA64MMFR2_EL1_AT_OFFSET) 2265 2266 /* 2267 * ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 2268 * 63 60 59 56 55 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2269 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 2270 * | CSV3 | CSV2 | RES0 | DIT | AMU | MPAM | SEL2 | SVE | RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | 2271 * +--------+--------+--------+-------+-------+--------+--------+-------+-------+-----+---------+------+-----+-----+-----+-----+ 2272 */ 2273 2274 #define ID_AA64PFR0_EL1_CSV3_OFFSET 60 2275 #define ID_AA64PFR0_EL1_CSV3_MASK (0xfull << ID_AA64PFR0_EL1_CSV3_OFFSET) 2276 #define ID_AA64PFR0_EL1_CSV3_EN (1ull << ID_AA64PFR0_EL1_CSV3_OFFSET) 2277 2278 #define ID_AA64PFR0_EL1_CSV2_OFFSET 56 2279 #define ID_AA64PFR0_EL1_CSV2_MASK (0xfull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2280 #define ID_AA64PFR0_EL1_CSV2_EN (1ull << ID_AA64PFR0_EL1_CSV2_OFFSET) 2281 2282 #define ID_AA64PFR0_EL1_DIT_OFFSET 48 2283 #define ID_AA64PFR0_EL1_DIT_MASK (0xfull << ID_AA64PFR0_EL1_DIT_OFFSET) 2284 #define ID_AA64PFR0_EL1_DIT_EN (1ull << ID_AA64PFR0_EL1_DIT_OFFSET) 2285 2286 #define ID_AA64PFR0_EL1_AdvSIMD_OFFSET 20 2287 #define ID_AA64PFR0_EL1_AdvSIMD_MASK (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2288 #define ID_AA64PFR0_EL1_AdvSIMD_HPFPCVT (0x0ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2289 #define ID_AA64PFR0_EL1_AdvSIMD_FP16 (0x1ull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2290 #define ID_AA64PFR0_EL1_AdvSIMD_DIS (0xfull << ID_AA64PFR0_EL1_AdvSIMD_OFFSET) 2291 2292 /* 2293 * ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 2294 * 63 20 19 16 15 12 11 8 7 4 3 0 2295 * +----------------------------------+-----------+----------+-------+------+------+ 2296 * | RES0 | MPAM_frac | RAS_frac | MTE | SSBS | BT | 2297 * +----------------------------------+-----------+----------+-------+------+------+ 2298 */ 2299 2300 2301 #define ID_AA64PFR1_EL1_SSBS_OFFSET 4 2302 #define ID_AA64PFR1_EL1_SSBS_MASK (0xfull << ID_AA64PFR1_EL1_SSBS_OFFSET) 2303 #define ID_AA64PFR1_EL1_SSBS_EN (1ull << ID_AA64PFR1_EL1_SSBS_OFFSET) 2304 2305 #define ID_AA64PFR1_EL1_BT_OFFSET 0 2306 #define ID_AA64PFR1_EL1_BT_MASK (0xfull << ID_AA64PFR1_EL1_BT_OFFSET) 2307 #define ID_AA64PFR1_EL1_BT_EN (1ull << ID_AA64PFR1_EL1_BT_OFFSET) 2308 2309 /* 2310 * ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 2311 * 2312 * 63 52 51 48 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 2313 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 2314 * | res0 | nTLBPA | AFP | HCX | ETS | TWED | XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS | 2315 * +------+--------+-----+-----+-----+-----+------+---------+-------+------+------+------+----------+--------+ 2316 */ 2317 2318 #define ID_AA64MMFR1_EL1_AFP_OFFSET 44 2319 #define ID_AA64MMFR1_EL1_AFP_MASK (0xfull << ID_AA64MMFR1_EL1_AFP_OFFSET) 2320 #define ID_AA64MMFR1_EL1_AFP_EN (1ull << ID_AA64MMFR1_EL1_AFP_OFFSET) 2321 2322 2323 2324 #define APSTATE_G_SHIFT (0) 2325 #define APSTATE_P_SHIFT (1) 2326 #define APSTATE_A_SHIFT (2) 2327 #define APSTATE_AP_MASK ((1ULL << APSTATE_A_SHIFT) | (1ULL << APSTATE_P_SHIFT)) 2328 2329 2330 #define ACTLR_EL1_EnTSO (1ULL << 1) 2331 #define ACTLR_EL1_EnAPFLG (1ULL << 4) 2332 #define ACTLR_EL1_EnAFP (1ULL << 5) 2333 #define ACTLR_EL1_EnPRSV (1ULL << 6) 2334 2335 2336 #if HAS_USAT_BIT 2337 #define ACTLR_EL1_USAT_OFFSET 0 2338 #define ACTLR_EL1_USAT_MASK (1ULL << ACTLR_EL1_USAT_OFFSET) 2339 #define ACTLR_EL1_USAT ACTLR_EL1_USAT_MASK 2340 #endif 2341 #define ACTLR_EL1_DisHWP_OFFSET 3 2342 #define ACTLR_EL1_DisHWP_MASK (1ULL << ACTLR_EL1_DisHWP_OFFSET) 2343 #define ACTLR_EL1_DisHWP ACTLR_EL1_DisHWP_MASK 2344 2345 2346 2347 2348 #if defined(HAS_APPLE_PAC) 2349 // The value of ptrauth_string_discriminator("recover"), hardcoded so it can be used from assembly code 2350 #define PAC_DISCRIMINATOR_RECOVER 0x1e02 2351 #endif 2352 2353 2354 #define CTR_EL0_L1Ip_OFFSET 14 2355 #define CTR_EL0_L1Ip_VIPT (2ULL << CTR_EL0_L1Ip_OFFSET) 2356 #define CTR_EL0_L1Ip_PIPT (3ULL << CTR_EL0_L1Ip_OFFSET) 2357 #define CTR_EL0_L1Ip_MASK (3ULL << CTR_EL0_L1Ip_OFFSET) 2358 2359 2360 #ifdef __ASSEMBLER__ 2361 2362 /* 2363 * Conditionally write to system/special-purpose register. 2364 * The register is written to only when the first two arguments 2365 * do not match. If they do match, the macro jumps to a 2366 * caller-provided label. 2367 * The _ISB variant also conditionally issues an ISB after the MSR. 2368 * 2369 * $0 - System/special-purpose register to modify 2370 * $1 - Register containing current FPCR value 2371 * $2 - Register containing expected value 2372 * $3 - Label to jump to when register is already set to expected value 2373 */ 2374 .macro CMSR 2375 cmp $1, $2 2376 2377 /* Skip expensive MSR if not required */ 2378 b.eq $3f 2379 msr $0, $2 2380 .endmacro 2381 2382 .macro CMSR_ISB 2383 CMSR $0, $1, $2, $3 2384 isb sy 2385 .endmacro 2386 2387 /* 2388 * Modify FPCR only if it does not contain the XNU default value. 2389 * $0 - Register containing current FPCR value 2390 * $1 - Scratch register 2391 * $2 - Label to jump to when FPCR is already set to default value 2392 */ 2393 .macro SANITIZE_FPCR 2394 mov $1, #FPCR_DEFAULT 2395 CMSR FPCR, $0, $1, $2 2396 .endmacro 2397 2398 /* 2399 * Family of macros that can be used to protect code sections such that they 2400 * are only executed on a particular SoC/Revision/CPU, and skipped otherwise. 2401 * All macros will forward-jump to 1f when the condition is not matched. 2402 * This label may be defined manually, or implicitly through the use of 2403 * the EXEC_END macro. 2404 * For cores, XX can be: EQ (equal), ALL (don't care). 2405 * For revisions, XX can be: EQ (equal), LO (lower than), HS (higher or same), ALL (don't care). 2406 */ 2407 2408 /* 2409 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 2410 * $1 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2411 * $2 - GPR containing MIDR_EL1 value 2412 * $3 - Scratch register 2413 */ 2414 .macro EXEC_COREEQ_REVEQ 2415 and $3, $2, #MIDR_EL1_PNUM_MASK 2416 cmp $3, $0 2417 b.ne 1f 2418 2419 mov $3, $2 2420 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2421 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2422 cmp $3, $1 2423 b.ne 1f 2424 .endmacro 2425 2426 .macro EXEC_COREEQ_REVLO 2427 and $3, $2, #MIDR_EL1_PNUM_MASK 2428 cmp $3, $0 2429 b.ne 1f 2430 2431 mov $3, $2 2432 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2433 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2434 cmp $3, $1 2435 b.pl 1f 2436 .endmacro 2437 2438 .macro EXEC_COREEQ_REVHS 2439 and $3, $2, #MIDR_EL1_PNUM_MASK 2440 cmp $3, $0 2441 b.ne 1f 2442 2443 mov $3, $2 2444 bfi $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #4 2445 ubfx $3, $3, #(MIDR_EL1_VAR_SHIFT - 4), #8 2446 cmp $3, $1 2447 b.mi 1f 2448 .endmacro 2449 2450 /* 2451 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2452 * $1 - GPR containing MIDR_EL1 value 2453 * $2 - Scratch register 2454 */ 2455 .macro EXEC_COREALL_REVEQ 2456 mov $2, $1 2457 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2458 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2459 cmp $2, $0 2460 b.ne 1f 2461 .endmacro 2462 2463 .macro EXEC_COREALL_REVLO 2464 mov $2, $1 2465 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2466 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2467 cmp $2, $0 2468 b.pl 1f 2469 .endmacro 2470 2471 .macro EXEC_COREALL_REVHS 2472 mov $2, $1 2473 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2474 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2475 cmp $2, $0 2476 b.mi 1f 2477 .endmacro 2478 2479 .macro CMP_FOREACH reg, cc, label, car, cdr:vararg 2480 cmp \reg, \car 2481 b.\cc \label 2482 .ifnb \cdr 2483 CMP_FOREACH \reg, \cc, \label, \cdr 2484 .endif 2485 .endm 2486 2487 .macro EXEC_COREIN_REVALL midr_el1, scratch, midr_list:vararg 2488 and \scratch, \midr_el1, #MIDR_EL1_PNUM_MASK 2489 CMP_FOREACH \scratch, eq, Lmatch\@, \midr_list 2490 b 1f 2491 Lmatch\@: 2492 .endm 2493 2494 /* 2495 * $0 - MIDR_SOC[_CORE], e.g. MIDR_ARUBA_VORTEX 2496 * $1 - GPR containing MIDR_EL1 value 2497 * $2 - Scratch register 2498 */ 2499 .macro EXEC_COREEQ_REVALL 2500 and $2, $1, #MIDR_EL1_PNUM_MASK 2501 cmp $2, $0 2502 b.ne 1f 2503 .endmacro 2504 2505 /* 2506 * $0 - CPU_VERSION_XX, e.g. CPU_VERSION_B1 2507 * $1 - GPR containing MIDR_EL1 value 2508 * $2 - Scratch register 2509 */ 2510 .macro EXEC_PCORE_REVEQ 2511 mrs $2, MPIDR_EL1 2512 and $2, $2, #(MPIDR_PNE) 2513 cmp $2, xzr 2514 b.eq 1f 2515 2516 mov $2, $1 2517 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2518 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2519 cmp $2, $0 2520 b.ne 1f 2521 .endmacro 2522 2523 .macro EXEC_PCORE_REVLO 2524 mrs $2, MPIDR_EL1 2525 and $2, $2, #(MPIDR_PNE) 2526 cmp $2, xzr 2527 b.eq 1f 2528 2529 mov $2, $1 2530 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2531 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2532 cmp $2, $0 2533 b.pl 1f 2534 .endmacro 2535 2536 .macro EXEC_PCORE_REVHS 2537 mrs $2, MPIDR_EL1 2538 and $2, $2, #(MPIDR_PNE) 2539 cmp $2, xzr 2540 b.eq 1f 2541 2542 mov $2, $1 2543 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2544 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2545 cmp $2, $0 2546 b.mi 1f 2547 .endmacro 2548 2549 .macro EXEC_ECORE_REVEQ 2550 mrs $2, MPIDR_EL1 2551 and $2, $2, #(MPIDR_PNE) 2552 cmp $2, xzr 2553 b.ne 1f 2554 2555 mov $2, $1 2556 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2557 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2558 cmp $2, $0 2559 b.ne 1f 2560 .endmacro 2561 2562 .macro EXEC_ECORE_REVLO 2563 mrs $2, MPIDR_EL1 2564 and $2, $2, #(MPIDR_PNE) 2565 cmp $2, xzr 2566 b.ne 1f 2567 2568 mov $2, $1 2569 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2570 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2571 cmp $2, $0 2572 b.pl 1f 2573 .endmacro 2574 2575 .macro EXEC_ECORE_REVHS 2576 mrs $2, MPIDR_EL1 2577 and $2, $2, #(MPIDR_PNE) 2578 cmp $2, xzr 2579 b.ne 1f 2580 2581 mov $2, $1 2582 bfi $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #4 2583 ubfx $2, $2, #(MIDR_EL1_VAR_SHIFT - 4), #8 2584 cmp $2, $0 2585 b.mi 1f 2586 .endmacro 2587 2588 /* 2589 * $0 - GPR containing MIDR_EL1 value 2590 * $1 - Scratch register 2591 */ 2592 .macro EXEC_PCORE_REVALL 2593 mrs $1, MPIDR_EL1 2594 and $1, $1, #(MPIDR_PNE) 2595 cmp $1, xzr 2596 b.eq 1f 2597 .endmacro 2598 2599 .macro EXEC_ECORE_REVALL 2600 mrs $1, MPIDR_EL1 2601 and $1, $1, #(MPIDR_PNE) 2602 cmp $1, xzr 2603 b.ne 1f 2604 .endmacro 2605 2606 2607 2608 /* 2609 * Macro that defines the label that all EXEC_COREXX_REVXX macros jump to. 2610 */ 2611 .macro EXEC_END 2612 1: 2613 .endmacro 2614 2615 /* 2616 * Wedges CPUs with a specified core that are below a specified revision. This 2617 * macro is intended for CPUs that have been deprecated in iBoot and may have 2618 * incorrect behavior if they continue running xnu. 2619 */ 2620 .macro DEPRECATE_COREEQ_REVLO core, rev, midr_el1, scratch 2621 EXEC_COREEQ_REVLO \core, \rev, \midr_el1, \scratch 2622 /* BEGIN IGNORE CODESTYLE */ 2623 b . 2624 /* END IGNORE CODESTYLE */ 2625 EXEC_END 2626 .endmacro 2627 2628 /* 2629 * Sets bits in an SPR register. 2630 * arg0: Name of the register to be accessed. 2631 * arg1: Mask of bits to be set. 2632 * arg2: Scratch register 2633 */ 2634 .macro HID_SET_BITS 2635 mrs $2, $0 2636 orr $2, $2, $1 2637 msr $0, $2 2638 .endmacro 2639 2640 /* 2641 * Clears bits in an SPR register. 2642 * arg0: Name of the register to be accessed. 2643 * arg1: Mask of bits to be cleared. 2644 * arg2: Scratch register 2645 */ 2646 .macro HID_CLEAR_BITS 2647 mrs $2, $0 2648 bic $2, $2, $1 2649 msr $0, $2 2650 .endmacro 2651 2652 /* 2653 * Combines the functionality of HID_CLEAR_BITS followed by HID_SET_BITS into 2654 * a single read-modify-write sequence. 2655 * arg0: Name of the register to be accessed. 2656 * arg1: Mask of bits to be cleared. 2657 * arg2: Value to insert 2658 * arg3: Scratch register 2659 */ 2660 .macro HID_INSERT_BITS 2661 mrs $3, $0 2662 bic $3, $3, $1 2663 orr $3, $3, $2 2664 msr $0, $3 2665 .endmacro 2666 2667 /* 2668 * Replaces the value of a field in an implementation-defined system register. 2669 * sreg: system register name 2670 * field: field name within the sysreg, where the assembler symbols 2671 * ARM64_REG_<field>_{shift,width} specify the bounds of the field 2672 * (note that preprocessor macros will not work here) 2673 * value: the value to insert 2674 * scr{1,2}: scratch regs 2675 */ 2676 .macro HID_WRITE_FIELD sreg, field, val, scr1, scr2 2677 mrs \scr1, \sreg 2678 mov \scr2, \val 2679 bfi \scr1, \scr2, ARM64_REG_\sreg\()_\field\()_shift, ARM64_REG_\sreg\()_\field\()_width 2680 msr \sreg, \scr1 2681 .endmacro 2682 2683 /* 2684 * Macro intended to be used as a replacement for ERET. 2685 * It prevents speculation past ERET instructions by padding 2686 * up to the decoder width. 2687 */ 2688 .macro ERET_CONTEXT_SYNCHRONIZING 2689 eret 2690 #if __ARM_SB_AVAILABLE__ 2691 sb // Technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 2692 #else /* __ARM_SB_AVAILABLE__ */ 2693 isb // ISB technically unnecessary on Apple micro-architectures, may restrict mis-speculation on other architectures 2694 nop // Sequence of six NOPs to pad out and terminate instruction decode group */ 2695 nop 2696 nop 2697 nop 2698 nop 2699 nop 2700 #endif /* !__ARM_SB_AVAILABLE__ */ 2701 .endmacro 2702 2703 2704 #endif /* __ASSEMBLER__ */ 2705 2706 #define MSR(reg, src) __asm__ volatile ("msr " reg ", %0" :: "r" (src)) 2707 #define MRS(dest, reg) __asm__ volatile ("mrs %0, " reg : "=r" (dest)) 2708 2709 #if XNU_MONITOR 2710 #define __ARM_PTE_PHYSMAP__ 1 2711 #define PPL_STATE_KERNEL 0 2712 #define PPL_STATE_DISPATCH 1 2713 #define PPL_STATE_PANIC 2 2714 #define PPL_STATE_EXCEPTION 3 2715 #endif 2716 2717 2718 #endif /* _ARM64_PROC_REG_H_ */ 2719