1 /* 2 * Copyright (c) 2023 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 29 #ifndef _PEXPERT_ARM64_H17_H 30 #define _PEXPERT_ARM64_H17_H 31 32 #define APPLEACC8 33 #define NO_MONITOR 1 /* No EL3 for this CPU -- ever */ 34 #define HAS_EL2 1 /* Has EL2 for this CPU */ 35 #define HAS_CTRR3 1 /* Has CTRRv3 registers */ 36 #define HAS_CONTINUOUS_HWCLOCK 1 /* Has a hardware clock that ticks during sleep */ 37 #define HAS_IPI 1 /* Has IPI registers */ 38 #define HAS_CLUSTER 1 /* Has eCores and pCores in separate clusters */ 39 #define HAS_RETENTION_STATE 1 /* Supports architectural state retention */ 40 #define HAS_DPC_ERR 1 /* Has an error register for DPC */ 41 #define HAS_UCNORMAL_MEM 1 /* Supports completely un-cacheable normal memory type */ 42 #define HAS_FAST_CNTVCT 1 43 #define HAS_E0PD 1 /* Supports E0PD0 and E0PD1 in TCR for Meltdown mitigation (ARMv8.5)*/ 44 #define HAS_ACFG 1 /* Supports ACFG_EL1 system register */ 45 #define HAS_AMDSCR 1 /* Supports AMDSCR_EL1 system register */ 46 #define HAS_HCR_TSC_RW 1 /* HCR_EL2.TSC is writable */ 47 #define HAS_APPLE_GENERIC_TIMER 1 /* Supports 24 MHz Apple timer */ 48 #define HAS_CPM_PWRDN_CTL 1 /* Supports CPM_PWRDN_CTL system register for deep sleep */ 49 #define HAS_EL1_SHAREABILITY_BOUNDARY 1 /* Supports shareability boundary on TLBI/SDSB instructions executed at EL1 */ 50 #define HAS_CPU_DPE_COUNTER 1 /* Has a hardware counter for digital power estimation */ 51 #define HAS_ACFG_DIS_DC_OPS 1 /* Has DCache maintenance op disable controls in ACFG_EL1 */ 52 #define HAS_16BIT_ASID 1 /* Supports 16-bit hardware ASIDs */ 53 #define HAS_FEAT_XS 1 /* Supports distinction between XS and non-XS memory transactions */ 54 #define HAS_DC_INCPA 1 /* Enable coprocessor cache flush */ 55 #define HAS_ARM_FEAT_SME 1 /* Supports ARM Scalable Matrix Extension */ 56 #define HAS_ARM_FEAT_SME2 1 /* Supports ARM Scalable Matrix Extension v2 */ 57 #define HAS_MTE 1 /* Platform has MTE support */ 58 #define NEEDS_MTE_IRG_RESEED 1 /* Platform has an IRG that needs reseeding on context switches */ 59 #define HAS_DISDDHWP0 1 /* Has Data-Dependent Hardware Prefetcher disablement bit. */ 60 #define HAS_GF2 1 /* Supports Galois Field Operations. */ 61 #define HAS_SPECRES 1 /* Supports SPECRES. */ 62 #define HAS_SPECRES2 1 /* Supports SPECRES2. */ 63 #define HAS_BTI 1 /* Supports Branch Target Identification (ARMv8.5) */ 64 #define HAS_GUARDED_IO_FILTER 1 /* Has a guarded runtime dedicated to the fine-grained IO access filter */ 65 66 #define CPU_HAS_APPLE_PAC 1 67 #define HAS_UNCORE_CTRS 1 68 #define UNCORE_VERSION 2 69 #define UNCORE_PER_CLUSTER 1 70 #define UNCORE_NCTRS 16 71 #define CORE_NCTRS 10 72 #define HAS_CPMU_PC_CAPTURE 1 73 74 /* Performance Monitor */ 75 #define CPMU_PMC_COUNT 10 76 #define CPMU_INSTRUCTION_MATCHING 1 77 #define CPMU_MEMORY_FILTERING 1 78 #define CPMU_64BIT_PMCS 1 79 #define CPMU_16BIT_EVENTS 1 80 #define HAS_UPMU 1 81 #define UPMU_VERSION 2 82 #define UPMU_PMC_COUNT 16 83 #define UPMU_PER_CLUSTER 1 84 #define UPMU_AF_LATENCY 1 85 #define UPMU_META_EVENTS 1 86 #define UPMU_64BIT_PMCS 1 87 #define UPMU_9BIT_SELECTORS 1 88 89 #define __ARM_AMP__ 1 90 #define __ARM_16K_PG__ 1 91 #define __ARM_GLOBAL_SLEEP_BIT__ 1 92 #define __ARM_PAN_AVAILABLE__ 1 93 #define __APPLE_WKDM_EXTENSIONS__ 1 94 #define __APPLE_WKDM_POPCNT_EXTENSIONS__ 1 95 #define __APPLE_WKDM_POPCNT_COMPRESSED_DATA__ 1 96 #define __ARM_SB_AVAILABLE__ 1 97 #define __PLATFORM_WKDM_ALIGNMENT_MASK__ (0x3FULL) 98 #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64) 99 100 #define __HWP_CFG_BIT_VER__ 2 101 102 /* Optional CPU features -- an SoC may #undef these */ 103 104 #define ARM_PARAMETERIZED_PMAP 1 105 #define __ARM_MIXED_PAGE_SIZE__ 1 106 107 #if !CONFIG_SPTM 108 /* VHE is disabled at runtime on SPTM-based systems. */ 109 #include <pexpert/arm64/vhe_disable.h> 110 #endif /* !CONFIG_SPTM */ 111 112 #include <pexpert/arm64/apple_arm64_common.h> 113 114 #endif /* !_PEXPERT_ARM64_H17_H */ 115