87 	uint_t		it_suffix:1;		/* mnem + "w", "l", or "d" */
90 	uint_t		it_size:16;
92 	uint_t		it_invalid64:1;		/* opcode invalid in amd64 */
93 	uint_t		it_always64:1;		/* 64 bit when in 64 bit mode */
94 	uint_t		it_invalid32:1;		/* invalid in IA32 */
95 	uint_t		it_stackop:1;		/* push/pop stack operation */
96 	uint_t		it_vexwoxmm:1;		/* VEX instructions that don't use XMM/YMM */
97 	uint_t		it_avxsuf:1;		/* AVX suffix required */
2351 	uint_t dgr_arg0;	/* src reg */
2352 	uint_t dgr_arg1;	/* vsib reg */
2353 	uint_t dgr_arg2;	/* dst reg */
2412 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)  in dtrace_get_opcode()
2438 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)  in dtrace_get_SIB()
2462 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)  in dtrace_get_modrm()
2477 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)  in dtrace_rex_adjust()
2497 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)  in dtrace_vex_adjust()
2521 	if (x->d86_numopnds < (uint_t)opindex + 1)  in dtrace_imm_opnd()
2522 		x->d86_numopnds = (uint_t)opindex + 1;  in dtrace_imm_opnd()
2622 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)  in dtrace_get_operand()
2625 	uint_t ss;		/* scale-factor from opcode */  in dtrace_get_operand()
2626 	uint_t index;		/* index register number */  in dtrace_get_operand()
2627 	uint_t base;		/* base register number */  in dtrace_get_operand()
2635 	if (x->d86_numopnds < (uint_t)opindex + 1)  in dtrace_get_operand()
2636 		x->d86_numopnds = (uint_t)opindex + 1;  in dtrace_get_operand()
2783 		uint_t need_paren = 0;  in dtrace_get_operand()
2903 dtrace_disx86(dis86_t *x, uint_t cpu_mode)  in dtrace_disx86()
2907 	uint_t i;  in dtrace_disx86()
2910 	uint_t nomem = 0;  in dtrace_disx86()
2915 	uint_t opnd_size;	/* SIZE16, SIZE32 or SIZE64 */  in dtrace_disx86()
2916 	uint_t addr_size;	/* SIZE16, SIZE32 or SIZE64 */  in dtrace_disx86()
2917 	uint_t wbit = 0;	/* opcode wbit, 0 is 8 bit, !0 for opnd_size */  in dtrace_disx86()
2918 	uint_t w2;		/* wbit value for second operand */  in dtrace_disx86()
2919 	uint_t vbit;  in dtrace_disx86()
2920 	uint_t mode = 0;	/* mode value from ModRM byte */  in dtrace_disx86()
2921 	uint_t reg = 0;		/* reg value from ModRM byte */  in dtrace_disx86()
2922 	uint_t r_m = 0;		/* r_m value from ModRM byte */  in dtrace_disx86()
2924 	uint_t opcode1 = 0;		/* high nibble of 1st byte */  in dtrace_disx86()
2925 	uint_t opcode2 = 0;		/* low nibble of 1st byte */  in dtrace_disx86()
2926 	uint_t opcode3 = 0;		/* extra opcode bits usually from ModRM byte */  in dtrace_disx86()
2927 	uint_t opcode4 = 0;		/* high nibble of 2nd byte */  in dtrace_disx86()
2928 	uint_t opcode5 = 0;		/* low nibble of 2nd byte */  in dtrace_disx86()
2929 	uint_t opcode6 = 0;		/* high nibble of 3rd byte */  in dtrace_disx86()
2930 	uint_t opcode7 = 0;		/* low nibble of 3rd byte */  in dtrace_disx86()
2931 	uint_t opcode_bytes = 1;  in dtrace_disx86()
2936 	uint_t	opnd_size_prefix = 0;  in dtrace_disx86()
2937 	uint_t	addr_size_prefix = 0;  in dtrace_disx86()
2938 	uint_t	segment_prefix = 0;  in dtrace_disx86()
2939 	uint_t	lock_prefix = 0;  in dtrace_disx86()
2940 	uint_t	rep_prefix = 0;  in dtrace_disx86()
2941 	uint_t	rex_prefix = 0;	/* amd64 register extension prefix */  in dtrace_disx86()
2948 	uint_t vex_prefix = 0;  in dtrace_disx86()
2954 	uint_t vex_byte1 = 0;  in dtrace_disx86()
2960 	uint_t vex_prefetch = 0;  in dtrace_disx86()
2962 	uint_t vex_m = 0;  in dtrace_disx86()
2963 	uint_t vex_v = 0;  in dtrace_disx86()
2964 	uint_t vex_p = 0;  in dtrace_disx86()
2965 	uint_t vex_R = 1;  in dtrace_disx86()
2966 	uint_t vex_X = 1;  in dtrace_disx86()
2967 	uint_t vex_B = 1;  in dtrace_disx86()
2968 	uint_t vex_W = 0;  in dtrace_disx86()
2969 	uint_t vex_L = 0;  in dtrace_disx86()
3031 		uint_t *which_prefix = NULL;  in dtrace_disx86()
3282 			uint_t	subcode;  in dtrace_disx86()
5461 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,  in dtrace_disx86_str()