Lines Matching refs:_HBit
62 #define _HBit(n) (1ULL << ((n)+32)) macro
98 #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
99 #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
100 #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
101 #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
102 #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
103 #define CPUID_FEATURE_VMX _HBit(5) /* VMX */
104 #define CPUID_FEATURE_SMX _HBit(6) /* SMX */
105 #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
106 #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
107 #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
108 #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
109 #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
110 #define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
111 #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
112 #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
113 #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
115 #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
116 #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
117 #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
118 #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
119 #define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
120 #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
121 #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
122 #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
123 #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
124 #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
125 #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
126 #define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
127 #define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */
128 #define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */
129 #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
165 #define CPUID_LEAF7_FEATURE_PREFETCHWT1 _HBit(0) /* Prefetch Write/T1 hint */
166 #define CPUID_LEAF7_FEATURE_AVX512VBMI _HBit(1) /* AVX512VBMI instructions */
167 #define CPUID_LEAF7_FEATURE_UMIP _HBit(2) /* User Mode Instruction Prevention */
168 #define CPUID_LEAF7_FEATURE_PKU _HBit(3) /* Protection Keys for Usermode */
169 #define CPUID_LEAF7_FEATURE_OSPKE _HBit(4) /* OS has enabled PKE */
170 #define CPUID_LEAF7_FEATURE_WAITPKG _HBit(5) /* WAITPKG instructions */
171 #define CPUID_LEAF7_FEATURE_GFNI _HBit(8) /* Galois Field New Instructions */
172 #define CPUID_LEAF7_FEATURE_VAES _HBit(9) /* Vector-encoded AES */
173 #define CPUID_LEAF7_FEATURE_VPCLMULQDQ _HBit(10) /* Vector Carryless-multiply */
174 #define CPUID_LEAF7_FEATURE_AVX512VNNI _HBit(11) /* AVX512 Vector Neural Net Instructions */
175 #define CPUID_LEAF7_FEATURE_AVX512BITALG _HBit(12) /* AVX512 VPOPCNT{B,W} and VPSHUFBITQMB */
176 #define CPUID_LEAF7_FEATURE_AVX512VPCDQ _HBit(14) /* AVX512 VPOPCNTDQ instruction */
177 #define CPUID_LEAF7_FEATURE_RDPID _HBit(22) /* RDPID and IA32_TSC_AUX */
178 #define CPUID_LEAF7_FEATURE_CLDEMOTE _HBit(25) /* Cache line demote */
179 #define CPUID_LEAF7_FEATURE_MOVDIRI _HBit(27) /* MOVDIRI instruction */
180 #define CPUID_LEAF7_FEATURE_MOVDIRI64B _HBit(28) /* MOVDIRI64B instruction */
181 #define CPUID_LEAF7_FEATURE_SGXLC _HBit(30) /* SGX Launch Configuration */
210 #define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */
211 #define CPUID_EXTFEATURE_LZCNT _HBit(5) /* LZCNT instruction */
212 #define CPUID_EXTFEATURE_PREFETCHW _HBit(8) /* PREFETCHW instruction */