Lines Matching refs:_Bit
61 #define _Bit(n) (1ULL << n) macro
68 #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
69 #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
70 #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
71 #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
72 #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
73 #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
74 #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
75 #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
76 #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
77 #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
78 #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
79 #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
80 #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
81 #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
82 #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
83 #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
84 #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
85 #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
86 #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
87 #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
88 #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
89 #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
90 #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
91 #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
92 #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
93 #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
94 #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
95 #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
96 #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
135 #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
136 #define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */
137 #define CPUID_LEAF7_FEATURE_SGX _Bit(2) /* Software Guard eXtensions */
138 #define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */
139 #define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/
140 #define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */
141 #define CPUID_LEAF7_FEATURE_FDPEO _Bit(6) /* x87 FPU Data Pointer updated only on x87 excep…
142 #define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
143 #define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */
144 #define CPUID_LEAF7_FEATURE_ERMS _Bit(9) /* Enhanced Rep Movsb/Stosb */
145 #define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */
146 #define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* RTM */
147 #define CPUID_LEAF7_FEATURE_PQM _Bit(12) /* Platform Qos Monitoring */
148 #define CPUID_LEAF7_FEATURE_FPU_CSDS _Bit(13) /* FPU CS/DS deprecation */
149 #define CPUID_LEAF7_FEATURE_MPX _Bit(14) /* Memory Protection eXtensions */
150 #define CPUID_LEAF7_FEATURE_PQE _Bit(15) /* Platform Qos Enforcement */
151 #define CPUID_LEAF7_FEATURE_AVX512F _Bit(16) /* AVX512F instructions */
152 #define CPUID_LEAF7_FEATURE_AVX512DQ _Bit(17) /* AVX512DQ instructions */
153 #define CPUID_LEAF7_FEATURE_RDSEED _Bit(18) /* RDSEED Instruction */
154 #define CPUID_LEAF7_FEATURE_ADX _Bit(19) /* ADX Instructions */
155 #define CPUID_LEAF7_FEATURE_SMAP _Bit(20) /* Supervisor Mode Access Protect */
156 #define CPUID_LEAF7_FEATURE_AVX512IFMA _Bit(21) /* AVX512IFMA instructions */
157 #define CPUID_LEAF7_FEATURE_CLFSOPT _Bit(23) /* CLFSOPT */
158 #define CPUID_LEAF7_FEATURE_CLWB _Bit(24) /* CLWB */
159 #define CPUID_LEAF7_FEATURE_IPT _Bit(25) /* Intel Processor Trace */
160 #define CPUID_LEAF7_FEATURE_AVX512CD _Bit(28) /* AVX512CD instructions */
161 #define CPUID_LEAF7_FEATURE_SHA _Bit(29) /* SHA instructions */
162 #define CPUID_LEAF7_FEATURE_AVX512BW _Bit(30) /* AVX512BW instructions */
163 #define CPUID_LEAF7_FEATURE_AVX512VL _Bit(31) /* AVX512VL instructions */
186 #define CPUID_LEAF7_EXTFEATURE_AVX5124VNNIW _Bit(2) /* AVX512_4VNNIW */
187 #define CPUID_LEAF7_EXTFEATURE_AVX5124FMAPS _Bit(3) /* AVX512_4FMAPS */
188 #define CPUID_LEAF7_EXTFEATURE_FSREPMOV _Bit(4) /* Fast Short REP MOV */
189 #define CPUID_LEAF7_EXTFEATURE_SRBDS_CTRL _Bit(9) /* SRBDS MSR Presence and Mitigatio…
190 #define CPUID_LEAF7_EXTFEATURE_MDCLEAR _Bit(10) /* Overloaded VERW / L1D_FLUSH */
191 #define CPUID_LEAF7_EXTFEATURE_TSXFA _Bit(13) /* TSX RTM_FORCE_ABORT MSR */
192 #define CPUID_LEAF7_EXTFEATURE_IBRS _Bit(26) /* IBRS / IBPB */
193 #define CPUID_LEAF7_EXTFEATURE_STIBP _Bit(27) /* Single Thread Indirect Branch Pr…
194 #define CPUID_LEAF7_EXTFEATURE_L1DF _Bit(28) /* L1D_FLUSH MSR */
195 #define CPUID_LEAF7_EXTFEATURE_ACAPMSR _Bit(29) /* ARCH_CAP MSR */
196 #define CPUID_LEAF7_EXTFEATURE_CCAPMSR _Bit(30) /* CORE_CAP MSR */
197 #define CPUID_LEAF7_EXTFEATURE_SSBD _Bit(31) /* Speculative Store Bypass Disable…
203 #define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
204 #define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
206 #define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */
207 #define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
208 #define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
218 #define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
242 #define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
243 #define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
295 #define CPUID_KVM_FEATURE_PV_UNHALT _Bit(7)
315 #define CPUID_LEAF_FEATURE_COREDUMP _Bit(0)
316 #define CPUID_LEAF_FEATURE_XNU_DEBUG _Bit(1)
317 #define CPUID_LEAF_FEATURE_MABS_OFFSET _Bit(2)
318 #define CPUID_LEAF_FEATURE_BOOTSESSIONUUID _Bit(3)