Lines Matching refs:CPU

68 `PSTATE.SM` moves the CPU in and out of a special execution mode called
72 things even more complicated, these transitions cause the CPU to zero out the
89 `PSTATE.{SM,ZA} = {0,0}` acts as a hint to the CPU that it may power down
110 case, the per-CPU `SMPRI_EL1` controls the relative priority of the SME
111 instructions issued by that CPU.  ARM guarantees that higher `SMPRI_EL1` values
150 become illegal while the CPU is in streaming SVE mode.  This poses a problem if
183 CPU's `PSTATE.ZA` bit is cleared (executing `smstop za` if necessary).  xnu does
185 thread: the next time `PSTATE.ZA` is enabled, the CPU is architecturally
203 Accordingly xnu resets `SMPRI_EL1` to `0` during CPU initialization, and
228 register state, xnu tries to keep the guest matrix state resident in the CPU as
292 * Access SME or SME2 state on a CPU that doesn't implement FEAT_SME or FEAT_SME2
379 depend on whether the CPU is in streaming SVE mode (described later in the
383 <a name="feat_sme_fa64_footnote"></a>2. The optional CPU feature FEAT_SME_FA64