Lines Matching refs:register

14 the length of the FPSIMD register files and adds new 1D vector-math
15 instructions.  SME extends SVE by adding a matrix register file and associated
17 instructions and register state.
33 SVE, SME, and SME2 introduce four new EL0-accessible register
41 These register files are unbanked, i.e., their contents are shared across all
44 can directly copy data between the vector and matrix register files.
46 Most of these register files supplement, rather than replace, the existing ARM
47 register files.  However the `Z` register file effectively extends the length of
48 the existing FPSIMD `V` register file.  Instructions targeting the `V` register
49 file will now access the lower 128 bits of the corresponding `Z` register.
52 (SVL), a power-of-two between 128 and 2048 inclusive.  Each `Z` register is SVL
53 bits in size; each `P` register is SVL / 8 bits in size; and `ZA` is SVL x SVL
60 SME also adds a single EL0-accessible system register `TPIDR2_EL0`.  Like
73 `V`/`Z` and `P` register files, and to set all `FPSR` flags.  When software
78 valid.  Setting `PSTATE.ZA` zeroes out both register files, and enables
95 - Reads or writes to the `SVCR` system register, which packs both bits into
96   a single register
119 trapping, by populating the lookup table register `SMPRIMAP_EL2` and setting the
131 - `SMEN`: trap SME instructions and register accesses, including SVE
133 - `FPEN`: trap FPSIMD, SME, and SVE instructions and most register accesses, but
170 build on lower-level routines to save and load SME register state, located in
186 guaranteed to zero out both register files.
192 or `P` register files, since these will be updated on kernel exit.
226 More critically, the `Z`, `P`, `ZA`, and `ZT0` register files are also shared
228 register state, xnu tries to keep the guest matrix state resident in the CPU as
256 register state are large and have implementation-defined size, accessing this
264 | `ARM_SVE_Z_STATE1`, `ARM_SME_Z_STATE2`       | `arm_sve_z_state_t`   | Z register file           |
265 | `ARM_SVE_P_STATE`                            | `arm_sve_p_state_t`   | P register file           |
266 | `ARM_SME_ZA_STATE1` ... `ARM_SME_ZA_STATE16` | `arm_sme_za_state_t`  | ZA register file          |
267 | `ARM_SME2_STATE`                             | `arm_sme2_state_t`    | ZT0 register file         |
278 register space into two different thread-state flavors.  Thread-state flavor
378 behavior on Apple CPUs.  Details like register length and accessibility may
388 discrete trap control `ZEN` for SVE instruction and register accesses performed