Lines Matching refs:as

20 to xnu.  It is not intended as a full programming guide for SVE or SME: readers
89 `PSTATE.{SM,ZA} = {0,0}` acts as a hint to the CPU that it may power down
90 SME-related hardware.  Hence software should clear these bits as soon as
121 executed at EL0 and EL1 will interpret `SMPRI_EL1` as an index into
122 `SMPRIMAP_EL2` rather than as a raw priority value.
138 as described above.  `SMIDR_EL1` accesses can trap to the hypervisor using the
168 implementation of `machine_switch_context()`, specifically as the routines
228 register state, xnu tries to keep the guest matrix state resident in the CPU as
229 long as possible, even when the guest traps to EL2.  xnu will only spill the `ZA`
299 exception messages.  Mach APIs that set exception ports, such as
306 `thread_get_state`.  (To keep the code as simple as possible, it ignores all of